Commit 4920a3a1 authored by Sujuan Chen's avatar Sujuan Chen Committed by Felix Fietkau
Browse files

wifi: mt76: mt7996: set DMA mask to 36 bits for boards with more than 4GB of RAM



Introduce the capability to run mt7996 driver on boards with more than
4GB of memory.

Co-developed-by: default avatarRex Lu <rex.lu@mediatek.com>
Signed-off-by: default avatarRex Lu <rex.lu@mediatek.com>
Signed-off-by: default avatarSujuan Chen <sujuan.chen@mediatek.com>
Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent 92184eae
Loading
Loading
Loading
Loading
+11 −1
Original line number Diff line number Diff line
@@ -232,8 +232,8 @@ mt76_dma_add_rx_buf(struct mt76_dev *dev, struct mt76_queue *q,
	struct mt76_queue_entry *entry = &q->entry[q->head];
	struct mt76_txwi_cache *txwi = NULL;
	struct mt76_desc *desc;
	u32 buf1 = 0, ctrl;
	int idx = q->head;
	u32 buf1 = 0, ctrl;
	int rx_token;

	if (mt76_queue_is_wed_rro_ind(q)) {
@@ -246,6 +246,9 @@ mt76_dma_add_rx_buf(struct mt76_dev *dev, struct mt76_queue *q,

	desc = &q->desc[q->head];
	ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
	buf1 = FIELD_PREP(MT_DMA_CTL_SDP0_H, buf->addr >> 32);
#endif

	if (mt76_queue_is_wed_rx(q)) {
		txwi = mt76_get_rxwi(dev);
@@ -312,11 +315,18 @@ mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
		entry->dma_len[0] = buf[0].len;

		ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
		info |= FIELD_PREP(MT_DMA_CTL_SDP0_H, buf[0].addr >> 32);
#endif
		if (i < nbufs - 1) {
			entry->dma_addr[1] = buf[1].addr;
			entry->dma_len[1] = buf[1].len;
			buf1 = buf[1].addr;
			ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
			info |= FIELD_PREP(MT_DMA_CTL_SDP1_H,
					   buf[1].addr >> 32);
#endif
			if (buf[1].skip_unmap)
				entry->skip_buf1 = true;
		}
+2 −0
Original line number Diff line number Diff line
@@ -19,6 +19,8 @@
#define MT_DMA_CTL_TO_HOST_A		BIT(12)
#define MT_DMA_CTL_DROP			BIT(14)
#define MT_DMA_CTL_TOKEN		GENMASK(31, 16)
#define MT_DMA_CTL_SDP1_H		GENMASK(19, 16)
#define MT_DMA_CTL_SDP0_H		GENMASK(3, 0)
#define MT_DMA_CTL_WO_DROP		BIT(8)

#define MT_DMA_PPE_CPU_REASON		GENMASK(15, 11)
+5 −2
Original line number Diff line number Diff line
@@ -142,8 +142,11 @@ u32 mt76_mmio_wed_init_rx_buf(struct mtk_wed_device *wed, int size)
			goto unmap;
		}

		desc->token |= cpu_to_le32(FIELD_PREP(MT_DMA_CTL_TOKEN,
						      token));
		token = FIELD_PREP(MT_DMA_CTL_TOKEN, token);
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
		token |= FIELD_PREP(MT_DMA_CTL_SDP0_H, addr >> 32);
#endif
		desc->token |= cpu_to_le32(token);
		desc++;
	}

+1 −1
Original line number Diff line number Diff line
@@ -183,7 +183,7 @@ struct mt76_queue_entry {
		struct urb *urb;
		int buf_sz;
	};
	u32 dma_addr[2];
	dma_addr_t dma_addr[2];
	u16 dma_len[2];
	u16 wcid;
	bool skip_buf0:1;
+3 −0
Original line number Diff line number Diff line
@@ -261,6 +261,9 @@ enum tx_mgnt_type {

#define MT_TXD9_WLAN_IDX		GENMASK(23, 8)

#define MT_TXP_BUF_LEN			GENMASK(11, 0)
#define MT_TXP_DMA_ADDR_H		GENMASK(15, 12)

#define MT_TX_RATE_STBC			BIT(14)
#define MT_TX_RATE_NSS			GENMASK(13, 10)
#define MT_TX_RATE_MODE			GENMASK(9, 6)
Loading