Commit 49947b90 authored by David Galiffi's avatar David Galiffi Committed by Alex Deucher
Browse files

drm/amd/display: Check if modulo is 0 before dividing. 



[How & Why]
If a value of 0 is read, then this will cause a divide-by-0 panic.

Reviewed-by: default avatarMartin Leung <Martin.Leung@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarDavid Galiffi <David.Galiffi@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3f69ee66

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

+6 −3
Original line number Diff line number Diff line
@@ -1101,9 +1101,12 @@ static bool get_pixel_clk_frequency_100hz( 
			 * not be programmed equal to DPREFCLK

			 */

			modulo_hz = REG_READ(MODULO[inst]);

			if (modulo_hz)

				*pixel_clk_khz = div_u64((uint64_t)clock_hz*

					clock_source->ctx->dc->clk_mgr->dprefclk_khz*10,

					modulo_hz);

			else

				*pixel_clk_khz = 0;

		} else {

			/* NOTE: There is agreement with VBIOS here that MODULO is

			 * programmed equal to DPREFCLK, in which case PHASE will be