Commit 49e41f3e authored by Alexei Lazar's avatar Alexei Lazar Committed by Leon Romanovsky
Browse files

net/mlx5: Add IFC bits for extended ETS rate limit bandwidth value 



Add hardware interface definitions to support extended bandwidth rate
limiting in the QoS Enhanced Transmission Selection (ETS) configuration.

The new fields include:
- max_bw_value: extended from 8-bit to 16-bit in ets_tcn_config_reg,
  simplifying the implementation by using a single field instead of
  separate MSB/LSB fields.
- qetcr_qshr_max_bw_val_msb: capability bit in qcam_qos_feature_cap_mask
  indicating device support for the extended 16-bit max_bw_value field.

These interface additions are prerequisites for increasing the per-TC
rate limit beyond 255 Gbps to support higher-bandwidth NICs.

Signed-off-by: default avatarAlexei Lazar <alazar@nvidia.com>
Reviewed-by: default avatarDragos Tatulea <dtatulea@nvidia.com>
Reviewed-by: default avatarGal Pressman <gal@nvidia.com>
Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1768200608-1543180-1-git-send-email-tariqt@nvidia.com


Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
parent f0b2fde9

include/linux/mlx5/mlx5_ifc.h

+4 −3
Original line number Diff line number Diff line
@@ -11009,7 +11009,9 @@ struct mlx5_ifc_qcam_access_reg_cap_mask { 
};



struct mlx5_ifc_qcam_qos_feature_cap_mask {

	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];

	u8         qcam_qos_feature_cap_mask_127_to_5[0x7B];

	u8         qetcr_qshr_max_bw_val_msb[0x1];

	u8         qcam_qos_feature_cap_mask_3_to_1[0x3];

	u8         qpts_trust_both[0x1];

};
@@ -11965,8 +11967,7 @@ struct mlx5_ifc_ets_tcn_config_reg_bits { 


	u8         reserved_at_20[0xc];

	u8         max_bw_units[0x4];

	u8         reserved_at_30[0x8];

	u8         max_bw_value[0x8];

	u8         max_bw_value[0x10];

};



struct mlx5_ifc_ets_global_config_reg_bits {