Commit 4a0f94df authored Jan 23, 2026 by Taimur Hassan Committed by Alex Deucher Feb 03, 2026

drm/amd/display: Promote DC to 3.2.368



This version brings along following fixes:
- Migrate DCCG register access from hwseq to dccg component.
- Add lpddr5 handling to dml2.1
- Correct external pr fsm control
- Make DCN35 OTG disable w/a reusable
- Make DSC FGCG a DSC block level function
- Make some DCN35 DCCG symbols reusable
- Fix writeback on DCN 3.2+
- Fix IGT link training failure on Replay panel
- Fix system resume lag issue
- Add oem panel config for new features
- Fix IGT ILR link training failure on Replay panel
- Fix a NULL pointer dereference in dcn20_hwseq.c
- Add Gfx Base Case For Linear Tiling Handling
- Migrate DIO registers access from hwseq to dio component.
- Match expected data types
- Add CRC 32-bit mode support for DCN3.6+
- Init DMUB DPIA Only for APU
- DIO memory leak fix.
- Add Handling for gfxversion DcGfxBase

Acked-by: ChiaHsuan Chung <chiahsuan.chung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 7c1ed3dc

drivers/gpu/drm/amd/display/dc/dc.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -63,7 +63,7 @@ struct dcn_dsc_reg_state;
		struct dcn_optc_reg_state;
		struct dcn_dccg_reg_state;

		#define DC_VER "3.2.367"
		#define DC_VER "3.2.368"

		/**
		* MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC