Commit 4a1d8aba authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-6.15-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V updates from Palmer Dabbelt:

 - The sub-architecture selection Kconfig system has been cleaned up,
   the documentation has been improved, and various detections have been
   fixed

 - The vector-related extensions dependencies are now validated when
   parsing from device tree and in the DT bindings

 - Misaligned access probing can be overridden via a kernel command-line
   parameter, along with various fixes to misalign access handling

 - Support for relocatable !MMU kernels builds

 - Support for hpge pfnmaps, which should improve TLB utilization

 - Support for runtime constants, which improves the d_hash()
   performance

 - Support for bfloat16, Zicbom, Zaamo, Zalrsc, Zicntr, Zihpm

 - Various fixes, including:
      - We were missing a secondary mmu notifier call when flushing the
        tlb which is required for IOMMU
      - Fix ftrace panics by saving the registers as expected by ftrace
      - Fix a couple of stimecmp usage related to cpu hotplug
      - purgatory_start is now aligned as per the STVEC requirements
      - A fix for hugetlb when calculating the size of non-present PTEs

* tag 'riscv-for-linus-6.15-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (65 commits)
  riscv: Add norvc after .option arch in runtime const
  riscv: Make sure toolchain supports zba before using zba instructions
  riscv/purgatory: 4B align purgatory_start
  riscv/kexec_file: Handle R_RISCV_64 in purgatory relocator
  selftests: riscv: fix v_exec_initval_nolibc.c
  riscv: Fix hugetlb retrieval of number of ptes in case of !present pte
  riscv: print hartid on bringup
  riscv: Add norvc after .option arch in runtime const
  riscv: Remove CONFIG_PAGE_OFFSET
  riscv: Support CONFIG_RELOCATABLE on riscv32
  asm-generic: Always define Elf_Rel and Elf_Rela
  riscv: Support CONFIG_RELOCATABLE on NOMMU
  riscv: Allow NOMMU kernels to access all of RAM
  riscv: Remove duplicate CONFIG_PAGE_OFFSET definition
  RISC-V: errata: Use medany for relocatable builds
  dt-bindings: riscv: document vector crypto requirements
  dt-bindings: riscv: add vector sub-extension dependencies
  dt-bindings: riscv: d requires f
  RISC-V: add f & d extension validation checks
  RISC-V: add vector crypto extension validation checks
  ...
parents 61f96e68 3eb64093
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+16 −0
Original line number Diff line number Diff line
@@ -7535,6 +7535,22 @@
			Note that genuine overcurrent events won't be
			reported either.

	unaligned_scalar_speed=
			[RISCV]
			Format: {slow | fast | unsupported}
			Allow skipping scalar unaligned access speed tests. This
			is useful for testing alternative code paths and to skip
			the tests in environments where they run too slowly. All
			CPUs must have the same scalar unaligned access speed.

	unaligned_vector_speed=
			[RISCV]
			Format: {slow | fast | unsupported}
			Allow skipping vector unaligned access speed tests. This
			is useful for testing alternative code paths and to skip
			the tests in environments where they run too slowly. All
			CPUs must have the same vector unaligned access speed.

	unknown_nmi_panic
			[X86] Cause panic on unknown NMI.

+32 −0
Original line number Diff line number Diff line
@@ -183,6 +183,9 @@ The following keys are defined:
       defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
       from commit 5059e0ca641c ("update to ratified").

  * :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0
       is supported as defined in the RISC-V ISA manual.

  * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as
       defined in the RISC-V Integer Conditional (Zicond) operations extension
       manual starting from commit 95cf1f9 ("Add changes requested by Ved
@@ -192,6 +195,9 @@ The following keys are defined:
       supported as defined in the RISC-V ISA manual starting from commit
       d8ab5c78c207 ("Zihintpause is ratified").

  * :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0
       is supported as defined in the RISC-V ISA manual.

  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
    supported, as defined by version 1.0 of the RISC-V Vector extension manual.

@@ -239,9 +245,32 @@ The following keys are defined:
       ratified in commit 98918c844281 ("Merge pull request #1217 from
       riscv/zawrs") of riscv-isa-manual.

  * :c:macro:`RISCV_HWPROBE_EXT_ZAAMO`: The Zaamo extension is supported as
       defined in the in the RISC-V ISA manual starting from commit e87412e621f1
       ("integrate Zaamo and Zalrsc text (#1304)").

  * :c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as
       defined in the in the RISC-V ISA manual starting from commit e87412e621f1
       ("integrate Zaamo and Zalrsc text (#1304)").

  * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as
       defined in version 1.0 of the RISC-V Pointer Masking extensions.

  * :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as
       defined in the RISC-V ISA manual starting from commit 4dc23d6229de
       ("Added Chapter title to BF16").

  * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as
       defined in the RISC-V ISA manual starting from commit 4dc23d6229de
       ("Added Chapter title to BF16").

  * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as
       defined in the RISC-V ISA manual starting from commit 4dc23d6229de
       ("Added Chapter title to BF16").

  * :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as
       ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.

* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to
     :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
     mistakenly classified as a bitmask rather than a value.
@@ -303,3 +332,6 @@ The following keys are defined:
    * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor
        extension is supported in the T-Head ISA extensions spec starting from
	commit a18c801634 ("Add T-Head VECTOR vendor extension. ").

* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which
  represents the size of the Zicbom block in bytes.
+149 −0
Original line number Diff line number Diff line
@@ -224,6 +224,12 @@ properties:
            as ratified at commit 4a69197e5617 ("Update to ratified state") of
            riscv-svvptc.

        - const: zaamo
          description: |
            The standard Zaamo extension for atomic memory operations as
            ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text
            (#1304)") of the unprivileged ISA specification.

        - const: zabha
          description: |
            The Zabha extension for Byte and Halfword Atomic Memory Operations
@@ -236,6 +242,12 @@ properties:
            is supported as ratified at commit 5059e0ca641c ("update to
            ratified") of the riscv-zacas.

        - const: zalrsc
          description: |
            The standard Zalrsc extension for load-reserved/store-conditional as
            ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text
            (#1304)") of the unprivileged ISA specification.

        - const: zawrs
          description: |
            The Zawrs extension for entering a low-power state or for trapping
@@ -329,6 +341,12 @@ properties:
            instructions, as ratified in commit 056b6ff ("Zfa is ratified") of
            riscv-isa-manual.

        - const: zfbfmin
          description:
            The standard Zfbfmin extension which provides minimal support for
            16-bit half-precision brain floating-point instructions, as ratified
            in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.

        - const: zfh
          description:
            The standard Zfh extension for 16-bit half-precision binary
@@ -525,6 +543,18 @@ properties:
            in commit 6f702a2 ("Vector extensions are now ratified") of
            riscv-v-spec.

        - const: zvfbfmin
          description:
            The standard Zvfbfmin extension for minimal support for vectored
            16-bit half-precision brain floating-point instructions, as ratified
            in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.

        - const: zvfbfwma
          description:
            The standard Zvfbfwma extension for vectored half-precision brain
            floating-point widening multiply-accumulate instructions, as ratified
            in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.

        - const: zvfh
          description:
            The standard Zvfh extension for vectored half-precision
@@ -639,6 +669,12 @@ properties:
            https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc.

    allOf:
      - if:
          contains:
            const: d
        then:
          contains:
            const: f
      # Zcb depends on Zca
      - if:
          contains:
@@ -673,6 +709,119 @@ properties:
        then:
          contains:
            const: zca
      # Zfbfmin depends on F
      - if:
          contains:
            const: zfbfmin
        then:
          contains:
            const: f
      # Zvfbfmin depends on V or Zve32f
      - if:
          contains:
            const: zvfbfmin
        then:
          oneOf:
            - contains:
                const: v
            - contains:
                const: zve32f
      # Zvfbfwma depends on Zfbfmin and Zvfbfmin
      - if:
          contains:
            const: zvfbfwma
        then:
          allOf:
            - contains:
                const: zfbfmin
            - contains:
                const: zvfbfmin
      # Zacas depends on Zaamo
      - if:
          contains:
            const: zacas
        then:
          contains:
            const: zaamo

      - if:
          contains:
            const: zve32x
        then:
          contains:
            const: zicsr

      - if:
          contains:
            const: zve32f
        then:
          allOf:
            - contains:
                const: f
            - contains:
                const: zve32x

      - if:
          contains:
            const: zve64x
        then:
          contains:
            const: zve32x

      - if:
          contains:
            const: zve64f
        then:
          allOf:
            - contains:
                const: f
            - contains:
                const: zve32f
            - contains:
                const: zve64x

      - if:
          contains:
            const: zve64d
        then:
          allOf:
            - contains:
                const: d
            - contains:
                const: zve64f

      - if:
          contains:
            anyOf:
              - const: zvbc
              - const: zvkn
              - const: zvknc
              - const: zvkng
              - const: zvknhb
              - const: zvksc
        then:
          contains:
            anyOf:
              - const: v
              - const: zve64x

      - if:
          contains:
            anyOf:
              - const: zvbb
              - const: zvkb
              - const: zvkg
              - const: zvkned
              - const: zvknha
              - const: zvksed
              - const: zvksh
              - const: zvks
              - const: zvkt
        then:
          contains:
            anyOf:
              - const: v
              - const: zve32x

allOf:
  # Zcf extension does not exist on rv64
+0 −1
Original line number Diff line number Diff line
# SPDX-License-Identifier: GPL-2.0-only

obj-y += kernel/ mm/ net/
obj-$(CONFIG_BUILTIN_DTB) += boot/dts/
obj-$(CONFIG_CRYPTO) += crypto/
obj-y += errata/
obj-$(CONFIG_KVM) += kvm/
+56 −28
Original line number Diff line number Diff line
@@ -65,6 +65,7 @@ config RISCV
	select ARCH_SUPPORTS_ATOMIC_RMW
	select ARCH_SUPPORTS_CFI_CLANG
	select ARCH_SUPPORTS_DEBUG_PAGEALLOC if MMU
	select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE
	select ARCH_SUPPORTS_HUGETLBFS if MMU
	# LLD >= 14: https://github.com/llvm/llvm-project/issues/50505
	select ARCH_SUPPORTS_LTO_CLANG if LLD_VERSION >= 140000
@@ -153,7 +154,7 @@ config RISCV
	select HAVE_DYNAMIC_FTRACE_WITH_ARGS if HAVE_DYNAMIC_FTRACE
	select HAVE_FTRACE_GRAPH_FUNC
	select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
	select HAVE_FUNCTION_GRAPH_TRACER
	select HAVE_FUNCTION_GRAPH_TRACER if HAVE_DYNAMIC_FTRACE_WITH_ARGS
	select HAVE_FUNCTION_GRAPH_FREGS
	select HAVE_FUNCTION_TRACER if !XIP_KERNEL && !PREEMPTION
	select HAVE_EBPF_JIT if MMU
@@ -205,6 +206,7 @@ config RISCV
	select PCI_DOMAINS_GENERIC if PCI
	select PCI_ECAM if (ACPI && PCI)
	select PCI_MSI if PCI
	select RELOCATABLE if !MMU && !PHYS_RAM_BASE_FIXED
	select RISCV_ALTERNATIVE if !XIP_KERNEL
	select RISCV_APLIC
	select RISCV_IMSIC
@@ -292,13 +294,6 @@ config MMU
	  Select if you want MMU-based virtualised addressing space
	  support by paged memory management. If unsure, say 'Y'.

config PAGE_OFFSET
	hex
	default 0x80000000 if !MMU && RISCV_M_MODE
	default 0x80200000 if !MMU
	default 0xc0000000 if 32BIT
	default 0xff60000000000000 if 64BIT

config KASAN_SHADOW_OFFSET
	hex
	depends on KASAN_GENERIC
@@ -570,7 +565,8 @@ config RISCV_ISA_C
	help
	  Adds "C" to the ISA subsets that the toolchain is allowed to emit
	  when building Linux, which results in compressed instructions in the
	  Linux binary.
	  Linux binary. This option produces a kernel that will not run on
	  systems that do not support compressed instructions.

	  If you don't know what to do here, say Y.

@@ -591,8 +587,8 @@ config RISCV_ISA_SVNAPOT
	depends on RISCV_ALTERNATIVE
	default y
	help
	  Allow kernel to detect the Svnapot ISA-extension dynamically at boot
	  time and enable its usage.
	  Enable support for the Svnapot ISA-extension when it is detected
	  at boot.

	  The Svnapot extension is used to mark contiguous PTEs as a range
	  of contiguous virtual-to-physical translations for a naturally
@@ -610,9 +606,8 @@ config RISCV_ISA_SVPBMT
	depends on RISCV_ALTERNATIVE
	default y
	help
	   Adds support to dynamically detect the presence of the Svpbmt
	   ISA-extension (Supervisor-mode: page-based memory types) and
	   enable its usage.
	   Add support for the Svpbmt ISA-extension (Supervisor-mode:
	   page-based memory types) in the kernel when it is detected at boot.

	   The memory type for a page contains a combination of attributes
	   that indicate the cacheability, idempotency, and ordering
@@ -631,14 +626,15 @@ config TOOLCHAIN_HAS_V
	depends on AS_HAS_OPTION_ARCH

config RISCV_ISA_V
	bool "VECTOR extension support"
	bool "Vector extension support"
	depends on TOOLCHAIN_HAS_V
	depends on FPU
	select DYNAMIC_SIGFRAME
	default y
	help
	  Say N here if you want to disable all vector related procedure
	  in the kernel.
	  Add support for the Vector extension when it is detected at boot.
	  When this option is disabled, neither the kernel nor userspace may
	  use vector procedures.

	  If you don't know what to do here, say Y.

@@ -737,6 +733,14 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO
	def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
	depends on AS_HAS_OPTION_ARCH

config TOOLCHAIN_HAS_ZBA
	bool
	default y
	depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
	depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
	depends on AS_HAS_OPTION_ARCH

config RISCV_ISA_ZBA
	bool "Zba extension support for bit manipulation instructions"
	default y
@@ -751,12 +755,12 @@ config RISCV_ISA_ZBA

config RISCV_ISA_ZBB
	bool "Zbb extension support for bit manipulation instructions"
	depends on TOOLCHAIN_HAS_ZBB
	depends on RISCV_ALTERNATIVE
	default y
	help
	   Adds support to dynamically detect the presence of the ZBB
	   extension (basic bit manipulation) and enable its usage.
	   Add support for enabling optimisations in the kernel when the
	   Zbb extension is detected at boot. Some optimisations may
	   additionally depend on toolchain support for Zbb.

	   The Zbb extension provides instructions to accelerate a number
	   of bit-specific operations (count bit population, sign extending,
@@ -787,6 +791,28 @@ config RISCV_ISA_ZBC

	   If you don't know what to do here, say Y.

config TOOLCHAIN_HAS_ZBKB
	bool
	default y
	depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbkb)
	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbkb)
	depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
	depends on AS_HAS_OPTION_ARCH

config RISCV_ISA_ZBKB
	bool "Zbkb extension support for bit manipulation instructions"
	depends on TOOLCHAIN_HAS_ZBKB
	depends on RISCV_ALTERNATIVE
	default y
	help
	   Adds support to dynamically detect the presence of the ZBKB
	   extension (bit manipulation for cryptography) and enable its usage.

	   The Zbkb extension provides instructions to accelerate a number
	   of common cryptography operations (pack, zip, etc).

	   If you don't know what to do here, say Y.

config RISCV_ISA_ZICBOM
	bool "Zicbom extension support for non-coherent DMA operation"
	depends on MMU
@@ -795,9 +821,9 @@ config RISCV_ISA_ZICBOM
	select RISCV_DMA_NONCOHERENT
	select DMA_DIRECT_REMAP
	help
	   Adds support to dynamically detect the presence of the ZICBOM
	   extension (Cache Block Management Operations) and enable its
	   usage.
	   Add support for the Zicbom extension (Cache Block Management
	   Operations) and enable its use in the kernel when it is detected
	   at boot.

	   The Zicbom extension can be used to handle for example
	   non-coherent DMA support on devices that need it.
@@ -810,7 +836,7 @@ config RISCV_ISA_ZICBOZ
	default y
	help
	   Enable the use of the Zicboz extension (cbo.zero instruction)
	   when available.
	   in the kernel when it is detected at boot.

	   The Zicboz extension is used for faster zeroing of memory.

@@ -848,8 +874,9 @@ config FPU
	bool "FPU support"
	default y
	help
	  Say N here if you want to disable all floating-point related procedure
	  in the kernel.
	  Add support for floating point operations when an FPU is detected at
	  boot. When this option is disabled, neither the kernel nor userspace
	  may use the floating point unit.

	  If you don't know what to do here, say Y.

@@ -1079,7 +1106,7 @@ config PARAVIRT_TIME_ACCOUNTING

config RELOCATABLE
	bool "Build a relocatable kernel"
	depends on MMU && 64BIT && !XIP_KERNEL
	depends on !XIP_KERNEL
	select MODULE_SECTIONS if MODULES
	help
          This builds a kernel as a Position Independent Executable (PIE),
@@ -1273,13 +1300,14 @@ config RISCV_ISA_FALLBACK
config BUILTIN_DTB
	bool "Built-in device tree"
	depends on OF && NONPORTABLE
	select GENERIC_BUILTIN_DTB
	help
	  Build a device tree into the Linux image.
	  This option should be selected if no bootloader is being used.
	  If unsure, say N.


config BUILTIN_DTB_SOURCE
config BUILTIN_DTB_NAME
	string "Built-in device tree source"
	depends on BUILTIN_DTB
	help
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