Unverified Commit 4a9b4e1f authored Jan 30, 2026 by Shuicheng Lin Committed by Rodrigo Vivi Feb 17, 2026

drm/xe/mmio: Avoid double-adjust in 64-bit reads



xe_mmio_read64_2x32() was adjusting register addresses and then
calling xe_mmio_read32(), which applies the adjustment again.
This may shift accesses twice if adj_offset < adj_limit. There is
no issue currently, as for media gt, adj_offset > adj_limit, so
the 2nd adjust will be a no-op. But it may not work in future.

To fix it, replace the adjusted-address comparison with a direct
sanity check that ensures the MMIO address adjustment cutoff never
falls within the 8-byte range of a 64-bit register. And let
xe_mmio_read32() handle address translation.

v2: rewrite the sanity check in a more natural way. (Matt)
v3: Add Fixes tag. (Jani)

Fixes: 07431945 ("drm/xe: Avoid 64-bit register reads")
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Shuicheng Lin <shuicheng.lin@intel.com>
Link: https://patch.msgid.link/20260130165621.471408-2-shuicheng.lin@intel.com


Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
(cherry picked from commit a30f9996)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

parent fbbe3261

drivers/gpu/drm/xe/xe_mmio.c

+5 −5

Original line number	Diff line number	Diff line
		@@ -256,11 +256,11 @@ u64 xe_mmio_read64_2x32(struct xe_mmio *mmio, struct xe_reg reg)
		struct xe_reg reg_udw = { .addr = reg.addr + 0x4 };
		u32 ldw, udw, oldudw, retries;

		reg.addr = xe_mmio_adjusted_addr(mmio, reg.addr);
		reg_udw.addr = xe_mmio_adjusted_addr(mmio, reg_udw.addr);

		/* we shouldn't adjust just one register address */
		xe_tile_assert(mmio->tile, reg_udw.addr == reg.addr + 0x4);
		/*
		* The two dwords of a 64-bit register can never straddle the offset
		* adjustment cutoff.
		*/
		xe_tile_assert(mmio->tile, !in_range(mmio->adj_limit, reg.addr + 1, 7));

		oldudw = xe_mmio_read32(mmio, reg_udw);
		for (retries = 5; retries; --retries) {