Commit 4adb9201 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'qcom-clk-for-6.13' of... 

Merge tag 'qcom-clk-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

 - Global clock controllers for Qualcomm QCS8300 and IPQ5424 SoCs
 - Camera, display and video clock controllers for Qualcomm SA8775P SoCs
 - Global, display, GPU, TCSR, and RPMh clock controllers for Qualcomm SAR2130P
 - Global, camera, display, GPU, and video clock controllers for
   Qualcomm SM8475 SoCs
 - Support for Qualcomm IPQ9574 in the Alpha PLL clock driver
 - Cleanup checks for already configured PLLs at boot in the Qualcomm
   Alpha PLL driver
 - Fix the initial rate for Qualcomm QCS404 GPLL3
 - Add shared rcg2 floor clk_ops for shared SDCC clks on Qualcomm SoCs

* tag 'qcom-clk-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (43 commits)
  clk: qcom: remove unused data from gcc-ipq5424.c
  clk: qcom: Add support for Global Clock Controller on QCS8300
  dt-bindings: clock: qcom: Add GCC clocks for QCS8300
  clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC
  clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574
  dt-bindings: clock: Add Qualcomm IPQ5424 GCC binding
  clk: qcom: add SAR2130P GPU Clock Controller support
  clk: qcom: dispcc-sm8550: enable support for SAR2130P
  clk: qcom: tcsrcc-sm8550: add SAR2130P support
  clk: qcom: add support for GCC on SAR2130P
  clk: qcom: rpmh: add support for SAR2130P
  clk: qcom: rcg2: add clk_rcg2_shared_floor_ops
  dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatibles
  dt-bindings: clock: qcom,sm8550-dispcc: Add SAR2130P compatible
  dt-bindings: clock: qcom,sm8550-tcsr: Add SAR2130P compatible
  dt-bindings: clock: qcom: document SAR2130P Global Clock Controller
  dt-bindings: clock: qcom,rpmhcc: Add SAR2130P compatible
  clk: qcom: Make GCC_6125 depend on QCOM_GDSC
  dt-bindings: clock: qcom: gcc-ipq9574: remove q6 bring up clock macros
  dt-bindings: clock: qcom: gcc-ipq5332: remove q6 bring up clock macros
  ...
parents 9852d85e f1f49cc5

Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml

+3 −1
Original line number Diff line number Diff line
@@ -17,7 +17,9 @@ description: | 


properties:

  compatible:

    const: qcom,gcc-sm8450

    enum:

      - qcom,gcc-sm8450

      - qcom,sm8475-gcc



  clocks:

    items:

Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml

+34 −7
Original line number Diff line number Diff line
@@ -4,31 +4,35 @@ 
$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on IPQ5332

title: Qualcomm Global Clock & Reset Controller on IPQ5332 and IPQ5424



maintainers:

  - Bjorn Andersson <andersson@kernel.org>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on IPQ5332.

  domains on IPQ5332 and IPQ5424.



  See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h



allOf:

  - $ref: qcom,gcc.yaml#

  See also:

    include/dt-bindings/clock/qcom,gcc-ipq5332.h

    include/dt-bindings/clock/qcom,gcc-ipq5424.h



properties:

  compatible:

    const: qcom,ipq5332-gcc

    enum:

      - qcom,ipq5332-gcc

      - qcom,ipq5424-gcc



  clocks:

    minItems: 5

    items:

      - description: Board XO clock source

      - description: Sleep clock source

      - description: PCIE 2lane PHY pipe clock source

      - description: PCIE 2lane x1 PHY pipe clock source (For second lane)

      - description: USB PCIE wrapper pipe clock source

      - description: PCIE 2-lane PHY2 pipe clock source

      - description: PCIE 2-lane PHY3 pipe clock source



  '#power-domain-cells': false

  '#interconnect-cells':
@@ -38,6 +42,29 @@ required: 
  - compatible

  - clocks



allOf:

  - $ref: qcom,gcc.yaml#

  - if:

      properties:

        compatible:

          contains:

            const: qcom,ipq5332-gcc

    then:

      properties:

        clocks:

          maxItems: 5



  - if:

      properties:

        compatible:

          contains:

            const: qcom,ipq5424-gcc

    then:

      properties:

        clocks:

          minItems: 7

          maxItems: 7



unevaluatedProperties: false



examples:

Documentation/devicetree/bindings/clock/qcom,qcs8300-gcc.yaml

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+66 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,qcs8300-gcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Technologies, Inc. Global Clock & Reset Controller on QCS8300



maintainers:

  - Taniya Das <quic_tdas@quicinc.com>

  - Imran Shaik <quic_imrashai@quicinc.com>



description: |

  Qualcomm Technologies, Inc. Global clock control module provides the clocks, resets and

  power domains on QCS8300



  See also: include/dt-bindings/clock/qcom,qcs8300-gcc.h



properties:

  compatible:

    const: qcom,qcs8300-gcc



  clocks:

    items:

      - description: Board XO source

      - description: Sleep clock source

      - description: PCIE 0 Pipe clock source

      - description: PCIE 1 Pipe clock source

      - description: PCIE Phy Auxiliary clock source

      - description: First EMAC controller reference clock

      - description: UFS Phy Rx symbol 0 clock source

      - description: UFS Phy Rx symbol 1 clock source

      - description: UFS Phy Tx symbol 0 clock source

      - description: USB3 Phy wrapper pipe clock source



required:

  - compatible

  - clocks

  - '#power-domain-cells'



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,qcs8300-gcc";

      reg = <0x00100000 0xc7018>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&sleep_clk>,

               <&pcie_0_pipe_clk>,

               <&pcie_1_pipe_clk>,

               <&pcie_phy_aux_clk>,

               <&rxc0_ref_clk>,

               <&ufs_phy_rx_symbol_0_clk>,

               <&ufs_phy_rx_symbol_1_clk>,

               <&ufs_phy_tx_symbol_0_clk>,

               <&usb3_phy_wrapper_gcc_usb30_prim_pipe_clk>;

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...

Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ properties: 
    enum:

      - qcom,qdu1000-rpmh-clk

      - qcom,sa8775p-rpmh-clk

      - qcom,sar2130p-rpmh-clk

      - qcom,sc7180-rpmh-clk

      - qcom,sc7280-rpmh-clk

      - qcom,sc8180x-rpmh-clk

Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,sa8775p-camcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Camera Clock & Reset Controller on SA8775P



maintainers:

  - Taniya Das <quic_tdas@quicinc.com>



description: |

  Qualcomm camera clock control module provides the clocks, resets and power

  domains on SA8775p.



  See also: include/dt-bindings/clock/qcom,sa8775p-camcc.h



properties:

  compatible:

    enum:

      - qcom,sa8775p-camcc



  clocks:

    items:

      - description: Camera AHB clock from GCC

      - description: Board XO source

      - description: Board active XO source

      - description: Sleep clock source



  power-domains:

    maxItems: 1

    description: MMCX power domain



required:

  - compatible

  - clocks

  - power-domains

  - '#power-domain-cells'



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/power/qcom-rpmpd.h>

    #include <dt-bindings/clock/qcom,sa8775p-gcc.h>

    clock-controller@ade0000 {

      compatible = "qcom,sa8775p-camcc";

      reg = <0x0ade0000 0x20000>;

      clocks = <&gcc GCC_CAMERA_AHB_CLK>,

               <&rpmhcc RPMH_CXO_CLK>,

               <&rpmhcc RPMH_CXO_CLK_A>,

               <&sleep_clk>;

      power-domains = <&rpmhpd SA8775P_MMCX>;

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...