Commit 4b2601ae authored by Praveen Talari's avatar Praveen Talari Committed by Greg Kroah-Hartman
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serial: qcom-geni: move resource initialization to separate function 



Enhances code readability and future modifications within the new API.

Move the code that handles the actual initialization of resources
like clock and ICC paths to a separate function, making the
probe function cleaner.

Reviewed-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: default avatarPraveen Talari <quic_ptalari@quicinc.com>
Link: https://lore.kernel.org/r/20250721174532.14022-5-quic_ptalari@quicinc.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent f5b16f28

drivers/tty/serial/qcom_geni_serial.c

+40 −26
Original line number Diff line number Diff line
@@ -1619,6 +1619,43 @@ static struct uart_driver qcom_geni_uart_driver = { 
	.nr =  GENI_UART_PORTS,

};



static int geni_serial_resource_init(struct qcom_geni_serial_port *port)

{

	int ret;



	port->se.clk = devm_clk_get(port->se.dev, "se");

	if (IS_ERR(port->se.clk)) {

		ret = PTR_ERR(port->se.clk);

		dev_err(port->se.dev, "Err getting SE Core clk %d\n", ret);

		return ret;

	}



	ret = geni_icc_get(&port->se, NULL);

	if (ret)

		return ret;



	port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;

	port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;



	/* Set BW for register access */

	ret = geni_icc_set_bw(&port->se);

	if (ret)

		return ret;



	ret = devm_pm_opp_set_clkname(port->se.dev, "se");

	if (ret)

		return ret;



	/* OPP table is optional */

	ret = devm_pm_opp_of_add_table(port->se.dev);

	if (ret && ret != -ENODEV) {

		dev_err(port->se.dev, "invalid OPP table in device tree\n");

		return ret;

	}



	return 0;

}



static void qcom_geni_serial_pm(struct uart_port *uport,

		unsigned int new_state, unsigned int old_state)

{
@@ -1739,12 +1776,10 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) 
	port->dev_data = data;

	port->se.dev = &pdev->dev;

	port->se.wrapper = dev_get_drvdata(pdev->dev.parent);

	port->se.clk = devm_clk_get(&pdev->dev, "se");

	if (IS_ERR(port->se.clk)) {

		ret = PTR_ERR(port->se.clk);

		dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);



	ret = geni_serial_resource_init(port);

	if (ret)

		return ret;

	}



	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (!res)
@@ -1764,17 +1799,6 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) 
			return -ENOMEM;

	}



	ret = geni_icc_get(&port->se, NULL);

	if (ret)

		return ret;

	port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;

	port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;



	/* Set BW for register access */

	ret = geni_icc_set_bw(&port->se);

	if (ret)

		return ret;



	port->name = devm_kasprintf(uport->dev, GFP_KERNEL,

			"qcom_geni_serial_%s%d",

			uart_console(uport) ? "console" : "uart", uport->line);
@@ -1796,16 +1820,6 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) 
	if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))

		port->cts_rts_swap = true;



	ret = devm_pm_opp_set_clkname(&pdev->dev, "se");

	if (ret)

		return ret;

	/* OPP table is optional */

	ret = devm_pm_opp_of_add_table(&pdev->dev);

	if (ret && ret != -ENODEV) {

		dev_err(&pdev->dev, "invalid OPP table in device tree\n");

		return ret;

	}



	port->private_data.drv = drv;

	uport->private_data = &port->private_data;

	platform_set_drvdata(pdev, port);