Commit 4b2769c7 authored by Krishna Kurapati's avatar Krishna Kurapati Committed by Bjorn Andersson
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arm64: dts: qcom: qcs615: Add primary USB interface 



Add support for primary USB controller and its PHYs on
QCS615.

Signed-off-by: default avatarKrishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241121063007.2737908-2-quic_kriskura@quicinc.com


[bjorn: Fixed subject]
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent f6746dc9

arch/arm64/boot/dts/qcom/qcs615.dtsi

+110 −0
Original line number Diff line number Diff line
@@ -430,6 +430,11 @@ qfprom: efuse@780000 { 
			reg = <0x0 0x00780000 0x0 0x7000>;

			#address-cells = <1>;

			#size-cells = <1>;



			qusb2_hstx_trim: hstx-trim@1f8 {

				reg = <0x1fb 0x1>;

				bits = <1 4>;

			};

		};



		gpi_dma0: dma-controller@800000  {
@@ -3035,6 +3040,111 @@ rpmhpd_opp_turbo_l1: opp-9 { 
				};

			};

		};



		usb_1_hsphy: phy@88e2000 {

			compatible = "qcom,qcs615-qusb2-phy";

			reg = <0x0 0x88e2000 0x0 0x180>;



			clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "cfg_ahb", "ref";



			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

			nvmem-cells = <&qusb2_hstx_trim>;



			#phy-cells = <0>;



			status = "disabled";

		};



		usb_qmpphy: phy@88e6000 {

			compatible = "qcom,qcs615-qmp-usb3-phy";

			reg = <0x0 0x88e6000 0x0 0x1000>;



			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,

				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,

				 <&gcc GCC_AHB2PHY_WEST_CLK>,

				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

			clock-names = "aux",

				      "ref",

				      "cfg_ahb",

				      "pipe";



			resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,

				 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;

			reset-names = "phy", "phy_phy";



			qcom,tcsr-reg = <&tcsr 0xb244>;



			clock-output-names = "usb3_phy_pipe_clk_src";

			#clock-cells = <0>;



			#phy-cells = <0>;



			status = "disabled";

		};



		usb_1: usb@a6f8800 {

			compatible = "qcom,qcs615-dwc3", "qcom,dwc3";

			reg = <0x0 0x0a6f8800 0x0 0x400>;



			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,

				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,

				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,

				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,

				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,

				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;

			clock-names = "cfg_noc",

				      "core",

				      "iface",

				      "sleep",

				      "mock_utmi",

				      "xo";



			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,

					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;

			assigned-clock-rates = <19200000>, <200000000>;



			interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,

					      <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,

					      <&pdc 9 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 8 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "pwr_event",

					  "hs_phy_irq",

					  "dp_hs_phy_irq",

					  "dm_hs_phy_irq",

					  "ss_phy_irq";



			power-domains = <&gcc USB30_PRIM_GDSC>;

			required-opps = <&rpmhpd_opp_nom>;



			resets = <&gcc GCC_USB30_PRIM_BCR>;



			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			status = "disabled";



			usb_1_dwc3: usb@a600000 {

				compatible = "snps,dwc3";

				reg = <0x0 0x0a600000 0x0 0xcd00>;



				iommus = <&apps_smmu 0x140 0x0>;

				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;



				phys = <&usb_1_hsphy>, <&usb_qmpphy>;

				phy-names = "usb2-phy", "usb3-phy";



				snps,dis-u1-entry-quirk;

				snps,dis-u2-entry-quirk;

				snps,dis_u2_susphy_quirk;

				snps,dis_enblslpm_quirk;

				snps,has-lpm-erratum;

				snps,hird-threshold = /bits/ 8 <0x10>;

				snps,usb3_lpm_capable;

			};

		};

	};



	arch_timer: timer {