Commit 4b7a59fa authored by Zenon Xiu's avatar Zenon Xiu Committed by Catalin Marinas
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Documentation/arm64: Fix the typo of register names 

The register name 'HWFGWTR_EL2' and 'HWFGRTR_EL2' is wrong, should be 'HFGWTR_EL2' and 'HFGRTR_EL2'.
Find the register description on arm website here,
https://developer.arm.com/documentation/ddi0601/2025-09/AArch64-Registers/HFGWTR-EL2--Hypervisor-Fine-Grained-Write-Trap-Register
https://developer.arm.com/documentation/ddi0601/2025-09/AArch64-Registers/HFGRTR-EL2--Hypervisor-Fine-Grained-Read-Trap-Register?lang=en



Signed-off-by: default avatarZenon Xiu <zenonxiu@outlook.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 3a866087

Documentation/arch/arm64/booting.rst

+4 −4
Original line number Diff line number Diff line
@@ -391,13 +391,13 @@ Before jumping into the kernel, the following conditions must be met: 
    - SMCR_EL2.LEN must be initialised to the same value for all CPUs the

      kernel will execute on.



    - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.

    - HFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.



    - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.

    - HFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.



    - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.

    - HFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.



    - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.

    - HFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.



  For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64):