Commit 4ba17aa4 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo
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wifi: rtw89: phy: generalize valid bit of BSS color 



The register fields of BSS color map and valid bit are in the same register
for existing chips, but coming WiFi 7 chips define another register to
set valid bit, so add a field to chip_info to reuse the code.

Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231016065115.751662-3-pkshih@realtek.com
parent 2901bbd2

drivers/net/wireless/realtek/rtw89/core.h

+1 −0
Original line number Diff line number Diff line
@@ -3711,6 +3711,7 @@ struct rtw89_chip_info { 
	u8 dcfo_comp_sft;

	const struct rtw89_imr_info *imr_info;

	const struct rtw89_rrsr_cfgs *rrsr_cfgs;

	struct rtw89_reg_def bss_clr_vld;

	u32 bss_clr_map_reg;

	u32 dma_ch_mask;

	u32 edcca_lvl_reg;

drivers/net/wireless/realtek/rtw89/phy.c

+2 −1
Original line number Diff line number Diff line
@@ -4636,6 +4636,7 @@ void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 
void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif)

{

	const struct rtw89_chip_info *chip = rtwdev->chip;

	const struct rtw89_reg_def *bss_clr_vld = &chip->bss_clr_vld;

	enum rtw89_phy_idx phy_idx = RTW89_PHY_0;

	u8 bss_color;
@@ -4644,7 +4645,7 @@ void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif 


	bss_color = vif->bss_conf.he_bss_color.color;



	rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_VLD0, 0x1,

	rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1,

			      phy_idx);

	rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT,

			      bss_color, phy_idx);

drivers/net/wireless/realtek/rtw89/rtw8851b.c

+1 −0
Original line number Diff line number Diff line
@@ -2438,6 +2438,7 @@ const struct rtw89_chip_info rtw8851b_chip_info = { 
	.dcfo_comp_sft		= 12,

	.imr_info		= &rtw8851b_imr_info,

	.rrsr_cfgs		= &rtw8851b_rrsr_cfgs,

	.bss_clr_vld		= {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0},

	.bss_clr_map_reg	= R_BSS_CLR_MAP_V1,

	.dma_ch_mask		= BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |

				  BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |

drivers/net/wireless/realtek/rtw89/rtw8852a.c

+1 −0
Original line number Diff line number Diff line
@@ -2175,6 +2175,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = { 
	.dcfo_comp_sft		= 10,

	.imr_info		= &rtw8852a_imr_info,

	.rrsr_cfgs		= &rtw8852a_rrsr_cfgs,

	.bss_clr_vld		= {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0},

	.bss_clr_map_reg	= R_BSS_CLR_MAP,

	.dma_ch_mask		= 0,

	.edcca_lvl_reg		= R_SEG0R_EDCCA_LVL,

drivers/net/wireless/realtek/rtw89/rtw8852b.c

+1 −0
Original line number Diff line number Diff line
@@ -2609,6 +2609,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = { 
	.dcfo_comp_sft		= 10,

	.imr_info		= &rtw8852b_imr_info,

	.rrsr_cfgs		= &rtw8852b_rrsr_cfgs,

	.bss_clr_vld		= {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0},

	.bss_clr_map_reg	= R_BSS_CLR_MAP_V1,

	.dma_ch_mask		= BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |

				  BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |