Unverified Commit 4bb5b6f1 authored by Vijendar Mukunda's avatar Vijendar Mukunda Committed by Mark Brown
Browse files

ASoC: amd: amd_sdw: Add quirks for Dell SKU's



This patch adds a quirk to include the codec amplifier function for Dell
SKU's listed in quirk table.

Note: In these SKU's, the RT722 codec amplifier is excluded, and an
external amplifier is used instead.

Signed-off-by: default avatarVijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://patch.msgid.link/20250207062819.1527184-26-Vijendar.Mukunda@amd.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 31e3100d
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+34 −0
Original line number Diff line number Diff line
@@ -28,6 +28,8 @@ static void log_quirks(struct device *dev)
			SOC_JACK_JDSRC(soc_sdw_quirk));
	if (soc_sdw_quirk & ASOC_SDW_ACP_DMIC)
		dev_dbg(dev, "quirk SOC_SDW_ACP_DMIC enabled\n");
	if (soc_sdw_quirk & ASOC_SDW_CODEC_SPKR)
		dev_dbg(dev, "quirk ASOC_SDW_CODEC_SPKR enabled\n");
}

static int soc_sdw_quirk_cb(const struct dmi_system_id *id)
@@ -45,6 +47,38 @@ static const struct dmi_system_id soc_sdw_quirk_table[] = {
		},
		.driver_data = (void *)RT711_JD2,
	},
	{
		.callback = soc_sdw_quirk_cb,
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0D80"),
		},
		.driver_data = (void *)(ASOC_SDW_CODEC_SPKR),
	},
	{
		.callback = soc_sdw_quirk_cb,
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0D81"),
		},
		.driver_data = (void *)(ASOC_SDW_CODEC_SPKR),
	},
	{
		.callback = soc_sdw_quirk_cb,
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0D82"),
		},
		.driver_data = (void *)(ASOC_SDW_CODEC_SPKR),
	},
	{
		.callback = soc_sdw_quirk_cb,
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0D83"),
		},
		.driver_data = (void *)(ASOC_SDW_CODEC_SPKR),
	},
	{}
};

+1 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@
#define SOC_JACK_JDSRC(quirk)		((quirk) & GENMASK(3, 0))
#define ASOC_SDW_FOUR_SPK		BIT(4)
#define ASOC_SDW_ACP_DMIC		BIT(5)
#define ASOC_SDW_CODEC_SPKR		BIT(15)

#define AMD_SDW0	0
#define AMD_SDW1	1