Commit 4c047c47 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sdm: change labels to lower-case 



DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-16-0505bc7d2c56@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 7b52cb20

arch/arm64/boot/dts/qcom/sdm630.dtsi

+76 −76
Original line number Diff line number Diff line
@@ -49,170 +49,170 @@ cpus { 
		#address-cells = <2>;

		#size-cells = <0>;



		CPU0: cpu@100 {

		cpu0: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x100>;

			enable-method = "psci";

			cpu-idle-states = <&PERF_CPU_SLEEP_0

						&PERF_CPU_SLEEP_1

						&PERF_CLUSTER_SLEEP_0

						&PERF_CLUSTER_SLEEP_1

						&PERF_CLUSTER_SLEEP_2>;

			cpu-idle-states = <&perf_cpu_sleep_0

						&perf_cpu_sleep_1

						&perf_cluster_sleep_0

						&perf_cluster_sleep_1

						&perf_cluster_sleep_2>;

			capacity-dmips-mhz = <1126>;

			#cooling-cells = <2>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

			next-level-cache = <&l2_1>;

			l2_1: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

			};

		};



		CPU1: cpu@101 {

		cpu1: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x101>;

			enable-method = "psci";

			cpu-idle-states = <&PERF_CPU_SLEEP_0

						&PERF_CPU_SLEEP_1

						&PERF_CLUSTER_SLEEP_0

						&PERF_CLUSTER_SLEEP_1

						&PERF_CLUSTER_SLEEP_2>;

			cpu-idle-states = <&perf_cpu_sleep_0

						&perf_cpu_sleep_1

						&perf_cluster_sleep_0

						&perf_cluster_sleep_1

						&perf_cluster_sleep_2>;

			capacity-dmips-mhz = <1126>;

			#cooling-cells = <2>;

			next-level-cache = <&L2_1>;

			next-level-cache = <&l2_1>;

		};



		CPU2: cpu@102 {

		cpu2: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x102>;

			enable-method = "psci";

			cpu-idle-states = <&PERF_CPU_SLEEP_0

						&PERF_CPU_SLEEP_1

						&PERF_CLUSTER_SLEEP_0

						&PERF_CLUSTER_SLEEP_1

						&PERF_CLUSTER_SLEEP_2>;

			cpu-idle-states = <&perf_cpu_sleep_0

						&perf_cpu_sleep_1

						&perf_cluster_sleep_0

						&perf_cluster_sleep_1

						&perf_cluster_sleep_2>;

			capacity-dmips-mhz = <1126>;

			#cooling-cells = <2>;

			next-level-cache = <&L2_1>;

			next-level-cache = <&l2_1>;

		};



		CPU3: cpu@103 {

		cpu3: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x103>;

			enable-method = "psci";

			cpu-idle-states = <&PERF_CPU_SLEEP_0

						&PERF_CPU_SLEEP_1

						&PERF_CLUSTER_SLEEP_0

						&PERF_CLUSTER_SLEEP_1

						&PERF_CLUSTER_SLEEP_2>;

			cpu-idle-states = <&perf_cpu_sleep_0

						&perf_cpu_sleep_1

						&perf_cluster_sleep_0

						&perf_cluster_sleep_1

						&perf_cluster_sleep_2>;

			capacity-dmips-mhz = <1126>;

			#cooling-cells = <2>;

			next-level-cache = <&L2_1>;

			next-level-cache = <&l2_1>;

		};



		CPU4: cpu@0 {

		cpu4: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x0>;

			enable-method = "psci";

			cpu-idle-states = <&PWR_CPU_SLEEP_0

						&PWR_CPU_SLEEP_1

						&PWR_CLUSTER_SLEEP_0

						&PWR_CLUSTER_SLEEP_1

						&PWR_CLUSTER_SLEEP_2>;

			cpu-idle-states = <&pwr_cpu_sleep_0

						&pwr_cpu_sleep_1

						&pwr_cluster_sleep_0

						&pwr_cluster_sleep_1

						&pwr_cluster_sleep_2>;

			capacity-dmips-mhz = <1024>;

			#cooling-cells = <2>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			next-level-cache = <&l2_0>;

			l2_0: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

			};

		};



		CPU5: cpu@1 {

		cpu5: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x1>;

			enable-method = "psci";

			cpu-idle-states = <&PWR_CPU_SLEEP_0

						&PWR_CPU_SLEEP_1

						&PWR_CLUSTER_SLEEP_0

						&PWR_CLUSTER_SLEEP_1

						&PWR_CLUSTER_SLEEP_2>;

			cpu-idle-states = <&pwr_cpu_sleep_0

						&pwr_cpu_sleep_1

						&pwr_cluster_sleep_0

						&pwr_cluster_sleep_1

						&pwr_cluster_sleep_2>;

			capacity-dmips-mhz = <1024>;

			#cooling-cells = <2>;

			next-level-cache = <&L2_0>;

			next-level-cache = <&l2_0>;

		};



		CPU6: cpu@2 {

		cpu6: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x2>;

			enable-method = "psci";

			cpu-idle-states = <&PWR_CPU_SLEEP_0

						&PWR_CPU_SLEEP_1

						&PWR_CLUSTER_SLEEP_0

						&PWR_CLUSTER_SLEEP_1

						&PWR_CLUSTER_SLEEP_2>;

			cpu-idle-states = <&pwr_cpu_sleep_0

						&pwr_cpu_sleep_1

						&pwr_cluster_sleep_0

						&pwr_cluster_sleep_1

						&pwr_cluster_sleep_2>;

			capacity-dmips-mhz = <1024>;

			#cooling-cells = <2>;

			next-level-cache = <&L2_0>;

			next-level-cache = <&l2_0>;

		};



		CPU7: cpu@3 {

		cpu7: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x3>;

			enable-method = "psci";

			cpu-idle-states = <&PWR_CPU_SLEEP_0

						&PWR_CPU_SLEEP_1

						&PWR_CLUSTER_SLEEP_0

						&PWR_CLUSTER_SLEEP_1

						&PWR_CLUSTER_SLEEP_2>;

			cpu-idle-states = <&pwr_cpu_sleep_0

						&pwr_cpu_sleep_1

						&pwr_cluster_sleep_0

						&pwr_cluster_sleep_1

						&pwr_cluster_sleep_2>;

			capacity-dmips-mhz = <1024>;

			#cooling-cells = <2>;

			next-level-cache = <&L2_0>;

			next-level-cache = <&l2_0>;

		};



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU4>;

					cpu = <&cpu4>;

				};



				core1 {

					cpu = <&CPU5>;

					cpu = <&cpu5>;

				};



				core2 {

					cpu = <&CPU6>;

					cpu = <&cpu6>;

				};



				core3 {

					cpu = <&CPU7>;

					cpu = <&cpu7>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&CPU0>;

					cpu = <&cpu0>;

				};



				core1 {

					cpu = <&CPU1>;

					cpu = <&cpu1>;

				};



				core2 {

					cpu = <&CPU2>;

					cpu = <&cpu2>;

				};



				core3 {

					cpu = <&CPU3>;

					cpu = <&cpu3>;

				};

			};

		};
@@ -220,7 +220,7 @@ core3 { 
		idle-states {

			entry-method = "psci";



			PWR_CPU_SLEEP_0: cpu-sleep-0-0 {

			pwr_cpu_sleep_0: cpu-sleep-0-0 {

				compatible = "arm,idle-state";

				idle-state-name = "pwr-retention";

				arm,psci-suspend-param = <0x40000002>;
@@ -229,7 +229,7 @@ PWR_CPU_SLEEP_0: cpu-sleep-0-0 { 
				min-residency-us = <200>;

			};



			PWR_CPU_SLEEP_1: cpu-sleep-0-1 {

			pwr_cpu_sleep_1: cpu-sleep-0-1 {

				compatible = "arm,idle-state";

				idle-state-name = "pwr-power-collapse";

				arm,psci-suspend-param = <0x40000003>;
@@ -239,7 +239,7 @@ PWR_CPU_SLEEP_1: cpu-sleep-0-1 { 
				local-timer-stop;

			};



			PERF_CPU_SLEEP_0: cpu-sleep-1-0 {

			perf_cpu_sleep_0: cpu-sleep-1-0 {

				compatible = "arm,idle-state";

				idle-state-name = "perf-retention";

				arm,psci-suspend-param = <0x40000002>;
@@ -248,7 +248,7 @@ PERF_CPU_SLEEP_0: cpu-sleep-1-0 { 
				min-residency-us = <200>;

			};



			PERF_CPU_SLEEP_1: cpu-sleep-1-1 {

			perf_cpu_sleep_1: cpu-sleep-1-1 {

				compatible = "arm,idle-state";

				idle-state-name = "perf-power-collapse";

				arm,psci-suspend-param = <0x40000003>;
@@ -258,7 +258,7 @@ PERF_CPU_SLEEP_1: cpu-sleep-1-1 { 
				local-timer-stop;

			};



			PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {

			pwr_cluster_sleep_0: cluster-sleep-0-0 {

				compatible = "arm,idle-state";

				idle-state-name = "pwr-cluster-dynamic-retention";

				arm,psci-suspend-param = <0x400000F2>;
@@ -268,7 +268,7 @@ PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { 
				local-timer-stop;

			};



			PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {

			pwr_cluster_sleep_1: cluster-sleep-0-1 {

				compatible = "arm,idle-state";

				idle-state-name = "pwr-cluster-retention";

				arm,psci-suspend-param = <0x400000F3>;
@@ -278,7 +278,7 @@ PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { 
				local-timer-stop;

			};



			PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {

			pwr_cluster_sleep_2: cluster-sleep-0-2 {

				compatible = "arm,idle-state";

				idle-state-name = "pwr-cluster-retention";

				arm,psci-suspend-param = <0x400000F4>;
@@ -288,7 +288,7 @@ PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { 
				local-timer-stop;

			};



			PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {

			perf_cluster_sleep_0: cluster-sleep-1-0 {

				compatible = "arm,idle-state";

				idle-state-name = "perf-cluster-dynamic-retention";

				arm,psci-suspend-param = <0x400000F2>;
@@ -298,7 +298,7 @@ PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { 
				local-timer-stop;

			};



			PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {

			perf_cluster_sleep_1: cluster-sleep-1-1 {

				compatible = "arm,idle-state";

				idle-state-name = "perf-cluster-retention";

				arm,psci-suspend-param = <0x400000F3>;
@@ -308,7 +308,7 @@ PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { 
				local-timer-stop;

			};



			PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {

			perf_cluster_sleep_2: cluster-sleep-1-2 {

				compatible = "arm,idle-state";

				idle-state-name = "perf-cluster-retention";

				arm,psci-suspend-param = <0x400000F4>;

arch/arm64/boot/dts/qcom/sdm660.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -85,49 +85,49 @@ opp-160000000 { 
	};

};



&CPU0 {

&cpu0 {

	compatible = "qcom,kryo260";

	capacity-dmips-mhz = <1024>;

	/delete-property/ operating-points-v2;

};



&CPU1 {

&cpu1 {

	compatible = "qcom,kryo260";

	capacity-dmips-mhz = <1024>;

	/delete-property/ operating-points-v2;

};



&CPU2 {

&cpu2 {

	compatible = "qcom,kryo260";

	capacity-dmips-mhz = <1024>;

	/delete-property/ operating-points-v2;

};



&CPU3 {

&cpu3 {

	compatible = "qcom,kryo260";

	capacity-dmips-mhz = <1024>;

	/delete-property/ operating-points-v2;

};



&CPU4 {

&cpu4 {

	compatible = "qcom,kryo260";

	capacity-dmips-mhz = <640>;

	/delete-property/ operating-points-v2;

};



&CPU5 {

&cpu5 {

	compatible = "qcom,kryo260";

	capacity-dmips-mhz = <640>;

	/delete-property/ operating-points-v2;

};



&CPU6 {

&cpu6 {

	compatible = "qcom,kryo260";

	capacity-dmips-mhz = <640>;

	/delete-property/ operating-points-v2;

};



&CPU7 {

&cpu7 {

	compatible = "qcom,kryo260";

	capacity-dmips-mhz = <640>;

	/delete-property/ operating-points-v2;

arch/arm64/boot/dts/qcom/sdm670.dtsi

+79 −79
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ cpus { 
		#address-cells = <2>;

		#size-cells = <0>;



		CPU0: cpu@0 {

		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "qcom,kryo360";

			reg = <0x0 0x0>;
@@ -43,15 +43,15 @@ CPU0: cpu@0 { 
			operating-points-v2 = <&cpu0_opp_table>;

			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,

					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			power-domains = <&CPU_PD0>;

			power-domains = <&cpu_pd0>;

			power-domain-names = "psci";

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			next-level-cache = <&l2_0>;

			l2_0: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

				cache-level = <2>;

				cache-unified;

				L3_0: l3-cache {

				l3_0: l3-cache {

					compatible = "cache";

					cache-level = <3>;

					cache-unified;
@@ -59,7 +59,7 @@ L3_0: l3-cache { 
			};

		};



		CPU1: cpu@100 {

		cpu1: cpu@100 {

			device_type = "cpu";

			compatible = "qcom,kryo360";

			reg = <0x0 0x100>;
@@ -70,18 +70,18 @@ CPU1: cpu@100 { 
			operating-points-v2 = <&cpu0_opp_table>;

			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,

					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			power-domains = <&CPU_PD1>;

			power-domains = <&cpu_pd1>;

			power-domain-names = "psci";

			next-level-cache = <&L2_100>;

			L2_100: l2-cache {

			next-level-cache = <&l2_100>;

			l2_100: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};

		};



		CPU2: cpu@200 {

		cpu2: cpu@200 {

			device_type = "cpu";

			compatible = "qcom,kryo360";

			reg = <0x0 0x200>;
@@ -92,18 +92,18 @@ CPU2: cpu@200 { 
			operating-points-v2 = <&cpu0_opp_table>;

			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,

					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			power-domains = <&CPU_PD2>;

			power-domains = <&cpu_pd2>;

			power-domain-names = "psci";

			next-level-cache = <&L2_200>;

			L2_200: l2-cache {

			next-level-cache = <&l2_200>;

			l2_200: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};

		};



		CPU3: cpu@300 {

		cpu3: cpu@300 {

			device_type = "cpu";

			compatible = "qcom,kryo360";

			reg = <0x0 0x300>;
@@ -114,18 +114,18 @@ CPU3: cpu@300 { 
			operating-points-v2 = <&cpu0_opp_table>;

			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,

					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			power-domains = <&CPU_PD3>;

			power-domains = <&cpu_pd3>;

			power-domain-names = "psci";

			next-level-cache = <&L2_300>;

			L2_300: l2-cache {

			next-level-cache = <&l2_300>;

			l2_300: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};

		};



		CPU4: cpu@400 {

		cpu4: cpu@400 {

			device_type = "cpu";

			compatible = "qcom,kryo360";

			reg = <0x0 0x400>;
@@ -136,18 +136,18 @@ CPU4: cpu@400 { 
			operating-points-v2 = <&cpu0_opp_table>;

			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,

					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			power-domains = <&CPU_PD4>;

			power-domains = <&cpu_pd4>;

			power-domain-names = "psci";

			next-level-cache = <&L2_400>;

			L2_400: l2-cache {

			next-level-cache = <&l2_400>;

			l2_400: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};

		};



		CPU5: cpu@500 {

		cpu5: cpu@500 {

			device_type = "cpu";

			compatible = "qcom,kryo360";

			reg = <0x0 0x500>;
@@ -158,18 +158,18 @@ CPU5: cpu@500 { 
			operating-points-v2 = <&cpu0_opp_table>;

			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,

					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			power-domains = <&CPU_PD5>;

			power-domains = <&cpu_pd5>;

			power-domain-names = "psci";

			next-level-cache = <&L2_500>;

			L2_500: l2-cache {

			next-level-cache = <&l2_500>;

			l2_500: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};

		};



		CPU6: cpu@600 {

		cpu6: cpu@600 {

			device_type = "cpu";

			compatible = "qcom,kryo360";

			reg = <0x0 0x600>;
@@ -180,18 +180,18 @@ CPU6: cpu@600 { 
			operating-points-v2 = <&cpu6_opp_table>;

			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,

					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			power-domains = <&CPU_PD6>;

			power-domains = <&cpu_pd6>;

			power-domain-names = "psci";

			next-level-cache = <&L2_600>;

			L2_600: l2-cache {

			next-level-cache = <&l2_600>;

			l2_600: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};

		};



		CPU7: cpu@700 {

		cpu7: cpu@700 {

			device_type = "cpu";

			compatible = "qcom,kryo360";

			reg = <0x0 0x700>;
@@ -202,49 +202,49 @@ CPU7: cpu@700 { 
			operating-points-v2 = <&cpu6_opp_table>;

			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,

					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			power-domains = <&CPU_PD7>;

			power-domains = <&cpu_pd7>;

			power-domain-names = "psci";

			next-level-cache = <&L2_700>;

			L2_700: l2-cache {

			next-level-cache = <&l2_700>;

			l2_700: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				cache-unified;

				next-level-cache = <&L3_0>;

				next-level-cache = <&l3_0>;

			};

		};



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU0>;

					cpu = <&cpu0>;

				};



				core1 {

					cpu = <&CPU1>;

					cpu = <&cpu1>;

				};



				core2 {

					cpu = <&CPU2>;

					cpu = <&cpu2>;

				};



				core3 {

					cpu = <&CPU3>;

					cpu = <&cpu3>;

				};



				core4 {

					cpu = <&CPU4>;

					cpu = <&cpu4>;

				};



				core5 {

					cpu = <&CPU5>;

					cpu = <&cpu5>;

				};



				core6 {

					cpu = <&CPU6>;

					cpu = <&cpu6>;

				};



				core7 {

					cpu = <&CPU7>;

					cpu = <&cpu7>;

				};

			};

		};
@@ -252,7 +252,7 @@ core7 { 
		idle-states {

			entry-method = "psci";



			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {

			little_cpu_sleep_0: cpu-sleep-0-0 {

				compatible = "arm,idle-state";

				idle-state-name = "little-rail-power-collapse";

				arm,psci-suspend-param = <0x40000004>;
@@ -262,7 +262,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 
				local-timer-stop;

			};



			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {

			big_cpu_sleep_0: cpu-sleep-1-0 {

				compatible = "arm,idle-state";

				idle-state-name = "big-rail-power-collapse";

				arm,psci-suspend-param = <0x40000004>;
@@ -274,7 +274,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 
		};



		domain-idle-states {

			CLUSTER_SLEEP_0: cluster-sleep-0 {

			cluster_sleep_0: cluster-sleep-0 {

				compatible = "domain-idle-state";

				arm,psci-suspend-param = <0x4100c244>;

				entry-latency-us = <3263>;
@@ -429,57 +429,57 @@ psci { 
		compatible = "arm,psci-1.0";

		method = "smc";



		CPU_PD0: power-domain-cpu0 {

		cpu_pd0: power-domain-cpu0 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&little_cpu_sleep_0>;

		};



		CPU_PD1: power-domain-cpu1 {

		cpu_pd1: power-domain-cpu1 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&little_cpu_sleep_0>;

		};



		CPU_PD2: power-domain-cpu2 {

		cpu_pd2: power-domain-cpu2 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&little_cpu_sleep_0>;

		};



		CPU_PD3: power-domain-cpu3 {

		cpu_pd3: power-domain-cpu3 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&little_cpu_sleep_0>;

		};



		CPU_PD4: power-domain-cpu4 {

		cpu_pd4: power-domain-cpu4 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&little_cpu_sleep_0>;

		};



		CPU_PD5: power-domain-cpu5 {

		cpu_pd5: power-domain-cpu5 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&little_cpu_sleep_0>;

		};



		CPU_PD6: power-domain-cpu6 {

		cpu_pd6: power-domain-cpu6 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&BIG_CPU_SLEEP_0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&big_cpu_sleep_0>;

		};



		CPU_PD7: power-domain-cpu7 {

		cpu_pd7: power-domain-cpu7 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&BIG_CPU_SLEEP_0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&big_cpu_sleep_0>;

		};



		CLUSTER_PD: power-domain-cluster {

		cluster_pd: power-domain-cluster {

			#power-domain-cells = <0>;

			domain-idle-states = <&CLUSTER_SLEEP_0>;

			domain-idle-states = <&cluster_sleep_0>;

		};

	};
@@ -1763,7 +1763,7 @@ apps_rsc: rsc@179c0000 { 
					  <SLEEP_TCS   3>,

					  <WAKE_TCS    3>,

					  <CONTROL_TCS 1>;

			power-domains = <&CLUSTER_PD>;

			power-domains = <&cluster_pd>;



			apps_bcm_voter: bcm-voter {

				compatible = "qcom,bcm-voter";

arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi

+37 −37
Original line number Diff line number Diff line
@@ -164,7 +164,7 @@ &cpus { 
};



&cpu_idle_states {

	LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {

	little_cpu_sleep_0: cpu-sleep-0-0 {

		compatible = "arm,idle-state";

		idle-state-name = "little-power-down";

		arm,psci-suspend-param = <0x40000003>;
@@ -174,7 +174,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 
		local-timer-stop;

	};



	LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {

	little_cpu_sleep_1: cpu-sleep-0-1 {

		compatible = "arm,idle-state";

		idle-state-name = "little-rail-power-down";

		arm,psci-suspend-param = <0x40000004>;
@@ -184,7 +184,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 
		local-timer-stop;

	};



	BIG_CPU_SLEEP_0: cpu-sleep-1-0 {

	big_cpu_sleep_0: cpu-sleep-1-0 {

		compatible = "arm,idle-state";

		idle-state-name = "big-power-down";

		arm,psci-suspend-param = <0x40000003>;
@@ -194,7 +194,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 
		local-timer-stop;

	};



	BIG_CPU_SLEEP_1: cpu-sleep-1-1 {

	big_cpu_sleep_1: cpu-sleep-1-1 {

		compatible = "arm,idle-state";

		idle-state-name = "big-rail-power-down";

		arm,psci-suspend-param = <0x40000004>;
@@ -204,7 +204,7 @@ BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 
		local-timer-stop;

	};



	CLUSTER_SLEEP_0: cluster-sleep-0 {

	cluster_sleep_0: cluster-sleep-0 {

		compatible = "arm,idle-state";

		idle-state-name = "cluster-power-down";

		arm,psci-suspend-param = <0x400000F4>;
@@ -215,68 +215,68 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { 
	};

};



&CPU0 {

&cpu0 {

	/delete-property/ power-domains;

	/delete-property/ power-domain-names;

	cpu-idle-states = <&LITTLE_CPU_SLEEP_0

			   &LITTLE_CPU_SLEEP_1

			   &CLUSTER_SLEEP_0>;

	cpu-idle-states = <&little_cpu_sleep_0

			   &little_cpu_sleep_1

			   &cluster_sleep_0>;

};



&CPU1 {

&cpu1 {

	/delete-property/ power-domains;

	/delete-property/ power-domain-names;

	cpu-idle-states = <&LITTLE_CPU_SLEEP_0

			   &LITTLE_CPU_SLEEP_1

			   &CLUSTER_SLEEP_0>;

	cpu-idle-states = <&little_cpu_sleep_0

			   &little_cpu_sleep_1

			   &cluster_sleep_0>;

};



&CPU2 {

&cpu2 {

	/delete-property/ power-domains;

	/delete-property/ power-domain-names;

	cpu-idle-states = <&LITTLE_CPU_SLEEP_0

			   &LITTLE_CPU_SLEEP_1

			   &CLUSTER_SLEEP_0>;

	cpu-idle-states = <&little_cpu_sleep_0

			   &little_cpu_sleep_1

			   &cluster_sleep_0>;

};



&CPU3 {

&cpu3 {

	/delete-property/ power-domains;

	/delete-property/ power-domain-names;

	cpu-idle-states = <&LITTLE_CPU_SLEEP_0

			   &LITTLE_CPU_SLEEP_1

			   &CLUSTER_SLEEP_0>;

	cpu-idle-states = <&little_cpu_sleep_0

			   &little_cpu_sleep_1

			   &cluster_sleep_0>;

};



&CPU4 {

&cpu4 {

	/delete-property/ power-domains;

	/delete-property/ power-domain-names;

	cpu-idle-states = <&BIG_CPU_SLEEP_0

			   &BIG_CPU_SLEEP_1

			   &CLUSTER_SLEEP_0>;

	cpu-idle-states = <&big_cpu_sleep_0

			   &big_cpu_sleep_1

			   &cluster_sleep_0>;

};



&CPU5 {

&cpu5 {

	/delete-property/ power-domains;

	/delete-property/ power-domain-names;

	cpu-idle-states = <&BIG_CPU_SLEEP_0

			   &BIG_CPU_SLEEP_1

			   &CLUSTER_SLEEP_0>;

	cpu-idle-states = <&big_cpu_sleep_0

			   &big_cpu_sleep_1

			   &cluster_sleep_0>;

};



&CPU6 {

&cpu6 {

	/delete-property/ power-domains;

	/delete-property/ power-domain-names;

	cpu-idle-states = <&BIG_CPU_SLEEP_0

			   &BIG_CPU_SLEEP_1

			   &CLUSTER_SLEEP_0>;

	cpu-idle-states = <&big_cpu_sleep_0

			   &big_cpu_sleep_1

			   &cluster_sleep_0>;

};



&CPU7 {

&cpu7 {

	/delete-property/ power-domains;

	/delete-property/ power-domain-names;

	cpu-idle-states = <&BIG_CPU_SLEEP_0

			   &BIG_CPU_SLEEP_1

			   &CLUSTER_SLEEP_0>;

	cpu-idle-states = <&big_cpu_sleep_0

			   &big_cpu_sleep_1

			   &cluster_sleep_0>;

};



&lmh_cluster0 {

arch/arm64/boot/dts/qcom/sdm845-db845c.dts

+2 −2
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ chosen { 
	};



	/* Fixed crystal oscillator dedicated to MCP2517FD */

	clk40M: can-clock {

	clk40m: can-clock {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <40000000>;
@@ -863,7 +863,7 @@ &spi0 { 
	can@0 {

		compatible = "microchip,mcp2517fd";

		reg = <0>;

		clocks = <&clk40M>;

		clocks = <&clk40m>;

		interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;

		spi-max-frequency = <10000000>;

		vdd-supply = <&vdc_5v>;