Commit 4c3b7df7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mtd/for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux 

Pull MTD updates from Miquel Raynal:
 "A big core MTD change is the introduction of a new class to always
  register a master device. This is a problem that has been there
  forever: the "master" device was not always present depending on a
  number of heuristics such as the presence of fixed partitions and the
  absence of a Kconfig symbol to force its presence. This was a problem
  for runtime PM operations which might not have the "master" device
  available in all situation.

  The SPI NAND subsystem has seen the introduction of DTR operations
  (the equivalent of DDR transfers), which involved quite a few
  preparation patches for clarifying macro names.

  In the raw NAND subsystem, the brcmnand driver has been "fixed" for
  old legacy SoCs with an update of the ->exec_op() hook, there has been
  the introduction of a new controller driver named Loongson-1, and the
  Qualcomm driver has received quite a few misc fixes as well as a new
  compatible.

  Finally, Macornix SPI NOR entries have been cleaned-up and some SFDP
  table fixups for Macronix MX25L3255E have been merged.

  Aside from this, there is the usual load of misc improvement, fixes,
  and yaml conversion"

* tag 'mtd/for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (42 commits)
  mtd: rawnand: brcmnand: legacy exec_op implementation
  mtd: rawnand: sunxi: Add randomizer configuration in sunxi_nfc_hw_ecc_write_chunk
  mtd: nand: brcmnand: fix NAND timeout when accessing eMMC
  mtd: nand: sunxi: Add randomizer configuration before randomizer enable
  mtd: spinand: esmt: fix id code for F50D1G41LB
  mtd: rawnand: brcmnand: remove unused parameters
  mtd: core: always create master device
  mtd: rawnand: loongson1: Fix inconsistent refcounting in ls1x_nand_chip_init()
  mtd: rawnand: loongson1: Fix error code in ls1x_nand_dma_transfer()
  mtd: rawnand: qcom: Fix read len for onfi param page
  mtd: rawnand: qcom: Fix last codeword read in qcom_param_page_type_exec()
  mtd: rawnand: qcom: Pass 18 bit offset from NANDc base to BAM base
  dt-bindings: mtd: qcom,nandc: Document the SDX75 NAND controller
  mtd: bcm47xxnflash: Add error handling for bcm47xxnflash_ops_bcm4706_ctl_cmd()
  mtd: rawnand: Use non-hybrid PCI devres API
  mtd: nand: ecc-mxic: Fix use of uninitialized variable ret
  mtd: spinand: winbond: Add support for W35N02JW and W35N04JW chips
  mtd: spinand: winbond: Add octal support
  mtd: spinand: winbond: Add support for W35N01JW in single mode
  mtd: spinand: winbond: Rename DTR variants
  ...
parents b509c16e aa702923

Documentation/devicetree/bindings/mtd/fsl,vf610-nfc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mtd/fsl,vf610-nfc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale's NAND flash controller (NFC)



description:

  This variant of the Freescale NAND flash controller (NFC) can be found on

  Vybrid (vf610), MPC5125, MCF54418 and Kinetis K70.



maintainers:

  - Frank Li <Frank.Li@nxp.com>



properties:

  compatible:

    enum:

      - fsl,vf610-nfc



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: nfc



patternProperties:

  "^nand@[a-f0-9]$":

    type: object

    $ref: raw-nand-chip.yaml



    properties:

      compatible:

        const: fsl,vf610-nfc-nandcs



      reg:

        const: 0



      nand-ecc-strength:

        enum: [24, 32]



      nand-ecc-step-size:

        const: 2048



    unevaluatedProperties: false



required:

  - compatible

  - reg

  - interrupts



allOf:

  - $ref: nand-controller.yaml



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/vf610-clock.h>



    nand-controller@400e0000 {

        compatible = "fsl,vf610-nfc";

        reg = <0x400e0000 0x4000>;

        #address-cells = <1>;

        #size-cells = <0>;

        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&clks VF610_CLK_NFC>;

        clock-names = "nfc";

        assigned-clocks = <&clks VF610_CLK_NFC>;

        assigned-clock-rates = <33000000>;



        nand@0 {

            compatible = "fsl,vf610-nfc-nandcs";

            reg = <0>;

            nand-bus-width = <8>;

            nand-ecc-mode = "hw";

            nand-ecc-strength = <32>;

            nand-ecc-step-size = <2048>;

            nand-on-flash-bbt;

        };

    };

Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mtd/loongson,ls1b-nand-controller.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Loongson-1 NAND Controller



maintainers:

  - Keguang Zhang <keguang.zhang@gmail.com>



description:

  The Loongson-1 NAND controller abstracts all supported operations,

  meaning it does not support low-level access to raw NAND flash chips.

  Moreover, the controller is paired with the DMA engine to perform

  READ and PROGRAM functions.



allOf:

  - $ref: nand-controller.yaml



properties:

  compatible:

    oneOf:

      - enum:

          - loongson,ls1b-nand-controller

          - loongson,ls1c-nand-controller

      - items:

          - enum:

              - loongson,ls1a-nand-controller

          - const: loongson,ls1b-nand-controller



  reg:

    maxItems: 2



  reg-names:

    items:

      - const: nand

      - const: nand-dma



  dmas:

    maxItems: 1



  dma-names:

    const: rxtx



required:

  - compatible

  - reg

  - reg-names

  - dmas

  - dma-names



unevaluatedProperties: false



examples:

  - |

    nand-controller@1fe78000 {

        compatible = "loongson,ls1b-nand-controller";

        reg = <0x1fe78000 0x24>, <0x1fe78040 0x4>;

        reg-names = "nand", "nand-dma";

        dmas = <&dma 0>;

        dma-names = "rxtx";

        #address-cells = <1>;

        #size-cells = <0>;



        nand@0 {

            reg = <0>;

            label = "ls1x-nand";

            nand-use-soft-ecc-engine;

            nand-ecc-algo = "hamming";

        };

    };

Documentation/devicetree/bindings/mtd/qcom,nandc.yaml

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@@ -11,7 +11,13 @@ maintainers: 


properties:

  compatible:

    enum:

    oneOf:

      - items:

          - enum:

              - qcom,sdx75-nand

          - const: qcom,sdx55-nand

      - items:

          - enum:

              - qcom,ipq806x-nand

              - qcom,ipq4019-nand

              - qcom,ipq6018-nand
@@ -95,6 +101,18 @@ allOf: 
          items:

            - const: rxtx



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sdx75-nand



    then:

      properties:

        iommus:

          maxItems: 1



  - if:

      properties:

        compatible:

Documentation/devicetree/bindings/mtd/vf610-nfc.txt

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Freescale's NAND flash controller (NFC)



This variant of the Freescale NAND flash controller (NFC) can be found on

Vybrid (vf610), MPC5125, MCF54418 and Kinetis K70.



Required properties:

- compatible: Should be set to "fsl,vf610-nfc".

- reg: address range of the NFC.

- interrupts: interrupt of the NFC.

- #address-cells: shall be set to 1. Encode the nand CS.

- #size-cells : shall be set to 0.

- assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;

- assigned-clock-rates: The NAND bus timing is derived from this clock

    rate and should not exceed maximum timing for any NAND memory chip

    in a board stuffing. Typical NAND memory timings derived from this

    clock are found in the SoC hardware reference manual. Furthermore,

    there might be restrictions on maximum rates when using hardware ECC.



- #address-cells, #size-cells : Must be present if the device has sub-nodes

  representing partitions.



Required children nodes:

Children nodes represent the available nand chips. Currently the driver can

only handle one NAND chip.



Required properties:

- compatible: Should be set to "fsl,vf610-nfc-cs".

- nand-bus-width: see nand-controller.yaml

- nand-ecc-mode: see nand-controller.yaml



Required properties for hardware ECC:

- nand-ecc-strength: supported strengths are 24 and 32 bit (see nand-controller.yaml)

- nand-ecc-step-size: step size equals page size, currently only 2k pages are

    supported

- nand-on-flash-bbt: see nand-controller.yaml



Example:



	nfc: nand@400e0000 {

		compatible = "fsl,vf610-nfc";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x400e0000 0x4000>;

		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&clks VF610_CLK_NFC>;

		clock-names = "nfc";

		assigned-clocks = <&clks VF610_CLK_NFC>;

		assigned-clock-rates = <33000000>;



		nand@0 {

			compatible = "fsl,vf610-nfc-nandcs";

			reg = <0>;

			nand-bus-width = <8>;

			nand-ecc-mode = "hw";

			nand-ecc-strength = <32>;

			nand-ecc-step-size = <2048>;

			nand-on-flash-bbt;

		};

	};

MAINTAINERS

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@@ -16589,6 +16589,7 @@ F: Documentation/devicetree/bindings/*/loongson,ls1*.yaml 
F:	arch/mips/include/asm/mach-loongson32/

F:	arch/mips/loongson32/

F:	drivers/*/*loongson1*

F:	drivers/mtd/nand/raw/loongson1-nand-controller.c

F:	drivers/net/ethernet/stmicro/stmmac/dwmac-loongson1.c

F:	sound/soc/loongson/loongson1_ac97.c