Commit 4c859574 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2024-04-04' of... 

Merge tag 'drm-intel-fixes-2024-04-04' of https://anongit.freedesktop.org/git/drm/drm-intel

 into drm-fixes

Display fixes:
- A few DisplayPort related fixes (Imre, Arun, Ankit, Ville)
- eDP PSR fixes (Jouni)

Core/GT fixes:
- Remove some VM space restrictions on older platforms (Andi)
- Disable automatic load CCS load balancing (Andi)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Zg7nSK5oTmWfKPPI@intel.com
parents a5b5ab33 99f85508

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -118,6 +118,7 @@ gt-y += \ 
	gt/intel_ggtt_fencing.o \

	gt/intel_gt.o \

	gt/intel_gt_buffer_pool.o \

	gt/intel_gt_ccs_mode.o \

	gt/intel_gt_clock_utils.o \

	gt/intel_gt_debugfs.o \

	gt/intel_gt_engines_debugfs.o \

drivers/gpu/drm/i915/display/intel_display.c

+0 −9
Original line number Diff line number Diff line
@@ -2709,15 +2709,6 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 
	 */

	intel_de_write(dev_priv, PIPESRC(pipe),

		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));



	if (!crtc_state->enable_psr2_su_region_et)

		return;



	width = drm_rect_width(&crtc_state->psr2_su_area);

	height = drm_rect_height(&crtc_state->psr2_su_area);



	intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe),

		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));

}



static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display_device.h

+1 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ struct drm_printer; 
#define HAS_DPT(i915)			(DISPLAY_VER(i915) >= 13)

#define HAS_DSB(i915)			(DISPLAY_INFO(i915)->has_dsb)

#define HAS_DSC(__i915)			(DISPLAY_RUNTIME_INFO(__i915)->has_dsc)

#define HAS_DSC_MST(__i915)		(DISPLAY_VER(__i915) >= 12 && HAS_DSC(__i915))

#define HAS_FBC(i915)			(DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)

#define HAS_FPGA_DBG_UNCLAIMED(i915)	(DISPLAY_INFO(i915)->has_fpga_dbg)

#define HAS_FW_BLC(i915)		(DISPLAY_VER(i915) >= 3)

drivers/gpu/drm/i915/display/intel_display_types.h

+2 −0
Original line number Diff line number Diff line
@@ -1423,6 +1423,8 @@ struct intel_crtc_state { 


	u32 psr2_man_track_ctl;



	u32 pipe_srcsz_early_tpt;



	struct drm_rect psr2_su_area;



	/* Variable Refresh Rate state */

drivers/gpu/drm/i915/display/intel_dp.c

+7 −4
Original line number Diff line number Diff line
@@ -499,7 +499,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) 
	/* The values must be in increasing order */

	static const int mtl_rates[] = {

		162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,

		810000,	1000000, 1350000, 2000000,

		810000,	1000000, 2000000,

	};

	static const int icl_rates[] = {

		162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
@@ -1422,7 +1422,8 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, 
	if (DISPLAY_VER(dev_priv) >= 12)

		return true;



	if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)

	if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A &&

	    !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))

		return true;



	return false;
@@ -1917,8 +1918,9 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp, 
	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);



	for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {

		if (valid_dsc_bpp[i] < dsc_min_bpp ||

		    valid_dsc_bpp[i] > dsc_max_bpp)

		if (valid_dsc_bpp[i] < dsc_min_bpp)

			continue;

		if (valid_dsc_bpp[i] > dsc_max_bpp)

			break;



		ret = dsc_compute_link_config(intel_dp,
@@ -6557,6 +6559,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, 
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;

	else

		intel_connector->get_hw_state = intel_connector_get_hw_state;

	intel_connector->sync_state = intel_dp_connector_sync_state;



	if (!intel_edp_init_connector(intel_dp, intel_connector)) {

		intel_dp_aux_fini(intel_dp);