Commit 4c8a7c98 authored by Tiezhu Yang's avatar Tiezhu Yang Committed by Huacai Chen
Browse files

LoongArch: Refine the init_hw_perf_events() function 

(1) Use the existing CPUCFG6_PMNUM_SHIFT macro definition instead of
the magic value 4 to get the PMU number.

(2) Detect the value of PMU bits via CPUCFG instruction according to
the ISA manual instead of hard-coded as 64, because the value may be
different for various micro-architectures.

Link: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_cpucfg


Signed-off-by: default avatarTiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
parent 17f83851

arch/loongarch/include/asm/loongarch.h

+1 −0
Original line number Diff line number Diff line
@@ -128,6 +128,7 @@ 
#define  CPUCFG6_PMNUM			GENMASK(7, 4)

#define  CPUCFG6_PMNUM_SHIFT		4

#define  CPUCFG6_PMBITS			GENMASK(13, 8)

#define  CPUCFG6_PMBITS_SHIFT		8

#define  CPUCFG6_UPM			BIT(14)



#define LOONGARCH_CPUCFG16		0x10

arch/loongarch/kernel/perf_event.c

+4 −3
Original line number Diff line number Diff line
@@ -845,13 +845,14 @@ static const struct loongarch_perf_event *loongarch_pmu_map_raw_event(u64 config 


static int __init init_hw_perf_events(void)

{

	int counters;

	int bits, counters;



	if (!cpu_has_pmp)

		return -ENODEV;



	pr_info("Performance counters: ");

	counters = ((read_cpucfg(LOONGARCH_CPUCFG6) & CPUCFG6_PMNUM) >> 4) + 1;

	bits = ((read_cpucfg(LOONGARCH_CPUCFG6) & CPUCFG6_PMBITS) >> CPUCFG6_PMBITS_SHIFT) + 1;

	counters = ((read_cpucfg(LOONGARCH_CPUCFG6) & CPUCFG6_PMNUM) >> CPUCFG6_PMNUM_SHIFT) + 1;



	loongarch_pmu.num_counters = counters;

	loongarch_pmu.max_period = (1ULL << 63) - 1;
@@ -867,7 +868,7 @@ static int __init init_hw_perf_events(void) 
	on_each_cpu(reset_counters, NULL, 1);



	pr_cont("%s PMU enabled, %d %d-bit counters available to each CPU.\n",

			loongarch_pmu.name, counters, 64);

			loongarch_pmu.name, counters, bits);



	perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);