Commit 4cb53fff authored by Jerome Brunet's avatar Jerome Brunet
Browse files

clk: amlogic: drop clk_regmap tables 

Remove the clk_regmap tables that are used to keep track which clock
need to be initialised before being registered. The initialisation is now
done by the .init() operation of clk_regmap.

This rework saves a bit memory and makes maintenance a bit easier.

Link: https://lore.kernel.org/r/20250623-amlogic-clk-drop-clk-regmap-tables-v4-2-ff04918211cc@baylibre.com


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 21ed19d1

drivers/clk/meson/a1-peripherals.c

+1 −162
Original line number Diff line number Diff line
@@ -2055,163 +2055,6 @@ static struct clk_hw *a1_periphs_hw_clks[] = { 
	[CLKID_DMC_SEL2]		= &dmc_sel2.hw,

};



/* Convenience table to populate regmap in .probe */

static struct clk_regmap *const a1_periphs_regmaps[] = {

	&xtal_in,

	&fixpll_in,

	&usb_phy_in,

	&usb_ctrl_in,

	&hifipll_in,

	&syspll_in,

	&dds_in,

	&sys,

	&clktree,

	&reset_ctrl,

	&analog_ctrl,

	&pwr_ctrl,

	&pad_ctrl,

	&sys_ctrl,

	&temp_sensor,

	&am2axi_dev,

	&spicc_b,

	&spicc_a,

	&msr,

	&audio,

	&jtag_ctrl,

	&saradc_en,

	&pwm_ef,

	&pwm_cd,

	&pwm_ab,

	&cec,

	&i2c_s,

	&ir_ctrl,

	&i2c_m_d,

	&i2c_m_c,

	&i2c_m_b,

	&i2c_m_a,

	&acodec,

	&otp,

	&sd_emmc_a,

	&usb_phy,

	&usb_ctrl,

	&sys_dspb,

	&sys_dspa,

	&dma,

	&irq_ctrl,

	&nic,

	&gic,

	&uart_c,

	&uart_b,

	&uart_a,

	&sys_psram,

	&rsa,

	&coresight,

	&am2axi_vad,

	&audio_vad,

	&axi_dmc,

	&axi_psram,

	&ramb,

	&rama,

	&axi_spifc,

	&axi_nic,

	&axi_dma,

	&cpu_ctrl,

	&rom,

	&prod_i2c,

	&dspa_sel,

	&dspb_sel,

	&dspa_en,

	&dspa_en_nic,

	&dspb_en,

	&dspb_en_nic,

	&rtc,

	&ceca_32k_out,

	&cecb_32k_out,

	&clk_24m,

	&clk_12m,

	&fclk_div2_divn,

	&gen,

	&saradc_sel,

	&saradc,

	&pwm_a,

	&pwm_b,

	&pwm_c,

	&pwm_d,

	&pwm_e,

	&pwm_f,

	&spicc,

	&ts,

	&spifc,

	&usb_bus,

	&sd_emmc,

	&psram,

	&dmc,

	&sys_a_sel,

	&sys_a_div,

	&sys_a,

	&sys_b_sel,

	&sys_b_div,

	&sys_b,

	&dspa_a_sel,

	&dspa_a_div,

	&dspa_a,

	&dspa_b_sel,

	&dspa_b_div,

	&dspa_b,

	&dspb_a_sel,

	&dspb_a_div,

	&dspb_a,

	&dspb_b_sel,

	&dspb_b_div,

	&dspb_b,

	&rtc_32k_in,

	&rtc_32k_div,

	&rtc_32k_xtal,

	&rtc_32k_sel,

	&cecb_32k_in,

	&cecb_32k_div,

	&cecb_32k_sel_pre,

	&cecb_32k_sel,

	&ceca_32k_in,

	&ceca_32k_div,

	&ceca_32k_sel_pre,

	&ceca_32k_sel,

	&fclk_div2_divn_pre,

	&gen_sel,

	&gen_div,

	&saradc_div,

	&pwm_a_sel,

	&pwm_a_div,

	&pwm_b_sel,

	&pwm_b_div,

	&pwm_c_sel,

	&pwm_c_div,

	&pwm_d_sel,

	&pwm_d_div,

	&pwm_e_sel,

	&pwm_e_div,

	&pwm_f_sel,

	&pwm_f_div,

	&spicc_sel,

	&spicc_div,

	&spicc_sel2,

	&ts_div,

	&spifc_sel,

	&spifc_div,

	&spifc_sel2,

	&usb_bus_sel,

	&usb_bus_div,

	&sd_emmc_sel,

	&sd_emmc_div,

	&sd_emmc_sel2,

	&psram_sel,

	&psram_div,

	&psram_sel2,

	&dmc_sel,

	&dmc_div,

	&dmc_sel2,

};



static const struct regmap_config a1_periphs_regmap_cfg = {

	.reg_bits   = 32,

	.val_bits   = 32,
@@ -2229,7 +2072,7 @@ static int meson_a1_periphs_probe(struct platform_device *pdev) 
	struct device *dev = &pdev->dev;

	void __iomem *base;

	struct regmap *map;

	int clkid, i, err;

	int clkid, err;



	base = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(base))
@@ -2241,10 +2084,6 @@ static int meson_a1_periphs_probe(struct platform_device *pdev) 
		return dev_err_probe(dev, PTR_ERR(map),

				     "can't init regmap mmio region\n");



	/* Populate regmap for the regmap backed clocks */

	for (i = 0; i < ARRAY_SIZE(a1_periphs_regmaps); i++)

		a1_periphs_regmaps[i]->map = map;



	for (clkid = 0; clkid < a1_periphs_clks.num; clkid++) {

		err = devm_clk_hw_register(dev, a1_periphs_clks.hws[clkid]);

		if (err)

drivers/clk/meson/a1-pll.c

+1 −15
Original line number Diff line number Diff line
@@ -295,16 +295,6 @@ static struct clk_hw *a1_pll_hw_clks[] = { 
	[CLKID_HIFI_PLL]	= &hifi_pll.hw,

};



static struct clk_regmap *const a1_pll_regmaps[] = {

	&fixed_pll_dco,

	&fixed_pll,

	&fclk_div2,

	&fclk_div3,

	&fclk_div5,

	&fclk_div7,

	&hifi_pll,

};



static const struct regmap_config a1_pll_regmap_cfg = {

	.reg_bits   = 32,

	.val_bits   = 32,
@@ -322,7 +312,7 @@ static int meson_a1_pll_probe(struct platform_device *pdev) 
	struct device *dev = &pdev->dev;

	void __iomem *base;

	struct regmap *map;

	int clkid, i, err;

	int clkid, err;



	base = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(base))
@@ -334,10 +324,6 @@ static int meson_a1_pll_probe(struct platform_device *pdev) 
		return dev_err_probe(dev, PTR_ERR(map),

				     "can't init regmap mmio region\n");



	/* Populate regmap for the regmap backed clocks */

	for (i = 0; i < ARRAY_SIZE(a1_pll_regmaps); i++)

		a1_pll_regmaps[i]->map = map;



	/* Register clocks */

	for (clkid = 0; clkid < a1_pll_clks.num; clkid++) {

		err = devm_clk_hw_register(dev, a1_pll_clks.hws[clkid]);

drivers/clk/meson/axg-aoclk.c

+0 −22
Original line number Diff line number Diff line
@@ -270,26 +270,6 @@ static const unsigned int axg_aoclk_reset[] = { 
	[RESET_AO_IR_BLASTER]	= 23,

};



static struct clk_regmap *axg_aoclk_regmap[] = {

	&axg_aoclk_remote,

	&axg_aoclk_i2c_master,

	&axg_aoclk_i2c_slave,

	&axg_aoclk_uart1,

	&axg_aoclk_uart2,

	&axg_aoclk_ir_blaster,

	&axg_aoclk_saradc,

	&axg_aoclk_cts_oscin,

	&axg_aoclk_32k_pre,

	&axg_aoclk_32k_div,

	&axg_aoclk_32k_sel,

	&axg_aoclk_32k,

	&axg_aoclk_cts_rtc_oscin,

	&axg_aoclk_clk81,

	&axg_aoclk_saradc_mux,

	&axg_aoclk_saradc_div,

	&axg_aoclk_saradc_gate,

};



static struct clk_hw *axg_aoclk_hw_clks[] = {

	[CLKID_AO_REMOTE]	= &axg_aoclk_remote.hw,

	[CLKID_AO_I2C_MASTER]	= &axg_aoclk_i2c_master.hw,
@@ -314,8 +294,6 @@ static const struct meson_aoclk_data axg_aoclkc_data = { 
	.reset_reg	= AO_RTI_GEN_CNTL_REG0,

	.num_reset	= ARRAY_SIZE(axg_aoclk_reset),

	.reset		= axg_aoclk_reset,

	.num_clks	= ARRAY_SIZE(axg_aoclk_regmap),

	.clks		= axg_aoclk_regmap,

	.hw_clks	= {

		.hws	= axg_aoclk_hw_clks,

		.num	= ARRAY_SIZE(axg_aoclk_hw_clks),

drivers/clk/meson/axg-audio.c

+0 −433
Original line number Diff line number Diff line
@@ -1311,427 +1311,6 @@ static struct clk_hw *sm1_audio_hw_clks[] = { 
	[AUD_CLKID_EARCRX_DMAC]		= &sm1_earcrx_dmac_clk.hw,

};





/* Convenience table to populate regmap in .probe(). */

static struct clk_regmap *const axg_clk_regmaps[] = {

	&ddr_arb,

	&pdm,

	&tdmin_a,

	&tdmin_b,

	&tdmin_c,

	&tdmin_lb,

	&tdmout_a,

	&tdmout_b,

	&tdmout_c,

	&frddr_a,

	&frddr_b,

	&frddr_c,

	&toddr_a,

	&toddr_b,

	&toddr_c,

	&loopback,

	&spdifin,

	&spdifout,

	&resample,

	&power_detect,

	&mst_a_mclk_sel,

	&mst_b_mclk_sel,

	&mst_c_mclk_sel,

	&mst_d_mclk_sel,

	&mst_e_mclk_sel,

	&mst_f_mclk_sel,

	&mst_a_mclk_div,

	&mst_b_mclk_div,

	&mst_c_mclk_div,

	&mst_d_mclk_div,

	&mst_e_mclk_div,

	&mst_f_mclk_div,

	&mst_a_mclk,

	&mst_b_mclk,

	&mst_c_mclk,

	&mst_d_mclk,

	&mst_e_mclk,

	&mst_f_mclk,

	&spdifout_clk_sel,

	&spdifout_clk_div,

	&spdifout_clk,

	&spdifin_clk_sel,

	&spdifin_clk_div,

	&spdifin_clk,

	&pdm_dclk_sel,

	&pdm_dclk_div,

	&pdm_dclk,

	&pdm_sysclk_sel,

	&pdm_sysclk_div,

	&pdm_sysclk,

	&mst_a_sclk_pre_en,

	&mst_b_sclk_pre_en,

	&mst_c_sclk_pre_en,

	&mst_d_sclk_pre_en,

	&mst_e_sclk_pre_en,

	&mst_f_sclk_pre_en,

	&mst_a_sclk_div,

	&mst_b_sclk_div,

	&mst_c_sclk_div,

	&mst_d_sclk_div,

	&mst_e_sclk_div,

	&mst_f_sclk_div,

	&mst_a_sclk_post_en,

	&mst_b_sclk_post_en,

	&mst_c_sclk_post_en,

	&mst_d_sclk_post_en,

	&mst_e_sclk_post_en,

	&mst_f_sclk_post_en,

	&mst_a_sclk,

	&mst_b_sclk,

	&mst_c_sclk,

	&mst_d_sclk,

	&mst_e_sclk,

	&mst_f_sclk,

	&mst_a_lrclk_div,

	&mst_b_lrclk_div,

	&mst_c_lrclk_div,

	&mst_d_lrclk_div,

	&mst_e_lrclk_div,

	&mst_f_lrclk_div,

	&mst_a_lrclk,

	&mst_b_lrclk,

	&mst_c_lrclk,

	&mst_d_lrclk,

	&mst_e_lrclk,

	&mst_f_lrclk,

	&tdmin_a_sclk_sel,

	&tdmin_b_sclk_sel,

	&tdmin_c_sclk_sel,

	&tdmin_lb_sclk_sel,

	&tdmout_a_sclk_sel,

	&tdmout_b_sclk_sel,

	&tdmout_c_sclk_sel,

	&tdmin_a_sclk_pre_en,

	&tdmin_b_sclk_pre_en,

	&tdmin_c_sclk_pre_en,

	&tdmin_lb_sclk_pre_en,

	&tdmout_a_sclk_pre_en,

	&tdmout_b_sclk_pre_en,

	&tdmout_c_sclk_pre_en,

	&tdmin_a_sclk_post_en,

	&tdmin_b_sclk_post_en,

	&tdmin_c_sclk_post_en,

	&tdmin_lb_sclk_post_en,

	&tdmout_a_sclk_post_en,

	&tdmout_b_sclk_post_en,

	&tdmout_c_sclk_post_en,

	&tdmin_a_sclk,

	&tdmin_b_sclk,

	&tdmin_c_sclk,

	&tdmin_lb_sclk,

	&axg_tdmout_a_sclk,

	&axg_tdmout_b_sclk,

	&axg_tdmout_c_sclk,

	&tdmin_a_lrclk,

	&tdmin_b_lrclk,

	&tdmin_c_lrclk,

	&tdmin_lb_lrclk,

	&tdmout_a_lrclk,

	&tdmout_b_lrclk,

	&tdmout_c_lrclk,

};



static struct clk_regmap *const g12a_clk_regmaps[] = {

	&ddr_arb,

	&pdm,

	&tdmin_a,

	&tdmin_b,

	&tdmin_c,

	&tdmin_lb,

	&tdmout_a,

	&tdmout_b,

	&tdmout_c,

	&frddr_a,

	&frddr_b,

	&frddr_c,

	&toddr_a,

	&toddr_b,

	&toddr_c,

	&loopback,

	&spdifin,

	&spdifout,

	&resample,

	&power_detect,

	&spdifout_b,

	&mst_a_mclk_sel,

	&mst_b_mclk_sel,

	&mst_c_mclk_sel,

	&mst_d_mclk_sel,

	&mst_e_mclk_sel,

	&mst_f_mclk_sel,

	&mst_a_mclk_div,

	&mst_b_mclk_div,

	&mst_c_mclk_div,

	&mst_d_mclk_div,

	&mst_e_mclk_div,

	&mst_f_mclk_div,

	&mst_a_mclk,

	&mst_b_mclk,

	&mst_c_mclk,

	&mst_d_mclk,

	&mst_e_mclk,

	&mst_f_mclk,

	&spdifout_clk_sel,

	&spdifout_clk_div,

	&spdifout_clk,

	&spdifin_clk_sel,

	&spdifin_clk_div,

	&spdifin_clk,

	&pdm_dclk_sel,

	&pdm_dclk_div,

	&pdm_dclk,

	&pdm_sysclk_sel,

	&pdm_sysclk_div,

	&pdm_sysclk,

	&mst_a_sclk_pre_en,

	&mst_b_sclk_pre_en,

	&mst_c_sclk_pre_en,

	&mst_d_sclk_pre_en,

	&mst_e_sclk_pre_en,

	&mst_f_sclk_pre_en,

	&mst_a_sclk_div,

	&mst_b_sclk_div,

	&mst_c_sclk_div,

	&mst_d_sclk_div,

	&mst_e_sclk_div,

	&mst_f_sclk_div,

	&mst_a_sclk_post_en,

	&mst_b_sclk_post_en,

	&mst_c_sclk_post_en,

	&mst_d_sclk_post_en,

	&mst_e_sclk_post_en,

	&mst_f_sclk_post_en,

	&mst_a_sclk,

	&mst_b_sclk,

	&mst_c_sclk,

	&mst_d_sclk,

	&mst_e_sclk,

	&mst_f_sclk,

	&mst_a_lrclk_div,

	&mst_b_lrclk_div,

	&mst_c_lrclk_div,

	&mst_d_lrclk_div,

	&mst_e_lrclk_div,

	&mst_f_lrclk_div,

	&mst_a_lrclk,

	&mst_b_lrclk,

	&mst_c_lrclk,

	&mst_d_lrclk,

	&mst_e_lrclk,

	&mst_f_lrclk,

	&tdmin_a_sclk_sel,

	&tdmin_b_sclk_sel,

	&tdmin_c_sclk_sel,

	&tdmin_lb_sclk_sel,

	&tdmout_a_sclk_sel,

	&tdmout_b_sclk_sel,

	&tdmout_c_sclk_sel,

	&tdmin_a_sclk_pre_en,

	&tdmin_b_sclk_pre_en,

	&tdmin_c_sclk_pre_en,

	&tdmin_lb_sclk_pre_en,

	&tdmout_a_sclk_pre_en,

	&tdmout_b_sclk_pre_en,

	&tdmout_c_sclk_pre_en,

	&tdmin_a_sclk_post_en,

	&tdmin_b_sclk_post_en,

	&tdmin_c_sclk_post_en,

	&tdmin_lb_sclk_post_en,

	&tdmout_a_sclk_post_en,

	&tdmout_b_sclk_post_en,

	&tdmout_c_sclk_post_en,

	&tdmin_a_sclk,

	&tdmin_b_sclk,

	&tdmin_c_sclk,

	&tdmin_lb_sclk,

	&g12a_tdmout_a_sclk,

	&g12a_tdmout_b_sclk,

	&g12a_tdmout_c_sclk,

	&tdmin_a_lrclk,

	&tdmin_b_lrclk,

	&tdmin_c_lrclk,

	&tdmin_lb_lrclk,

	&tdmout_a_lrclk,

	&tdmout_b_lrclk,

	&tdmout_c_lrclk,

	&spdifout_b_clk_sel,

	&spdifout_b_clk_div,

	&spdifout_b_clk,

	&g12a_tdm_mclk_pad_0,

	&g12a_tdm_mclk_pad_1,

	&g12a_tdm_lrclk_pad_0,

	&g12a_tdm_lrclk_pad_1,

	&g12a_tdm_lrclk_pad_2,

	&g12a_tdm_sclk_pad_0,

	&g12a_tdm_sclk_pad_1,

	&g12a_tdm_sclk_pad_2,

	&toram,

	&eqdrc,

};



static struct clk_regmap *const sm1_clk_regmaps[] = {

	&ddr_arb,

	&pdm,

	&tdmin_a,

	&tdmin_b,

	&tdmin_c,

	&tdmin_lb,

	&tdmout_a,

	&tdmout_b,

	&tdmout_c,

	&frddr_a,

	&frddr_b,

	&frddr_c,

	&toddr_a,

	&toddr_b,

	&toddr_c,

	&loopback,

	&spdifin,

	&spdifout,

	&resample,

	&spdifout_b,

	&sm1_mst_a_mclk_sel,

	&sm1_mst_b_mclk_sel,

	&sm1_mst_c_mclk_sel,

	&sm1_mst_d_mclk_sel,

	&sm1_mst_e_mclk_sel,

	&sm1_mst_f_mclk_sel,

	&sm1_mst_a_mclk_div,

	&sm1_mst_b_mclk_div,

	&sm1_mst_c_mclk_div,

	&sm1_mst_d_mclk_div,

	&sm1_mst_e_mclk_div,

	&sm1_mst_f_mclk_div,

	&sm1_mst_a_mclk,

	&sm1_mst_b_mclk,

	&sm1_mst_c_mclk,

	&sm1_mst_d_mclk,

	&sm1_mst_e_mclk,

	&sm1_mst_f_mclk,

	&spdifout_clk_sel,

	&spdifout_clk_div,

	&spdifout_clk,

	&spdifin_clk_sel,

	&spdifin_clk_div,

	&spdifin_clk,

	&pdm_dclk_sel,

	&pdm_dclk_div,

	&pdm_dclk,

	&pdm_sysclk_sel,

	&pdm_sysclk_div,

	&pdm_sysclk,

	&mst_a_sclk_pre_en,

	&mst_b_sclk_pre_en,

	&mst_c_sclk_pre_en,

	&mst_d_sclk_pre_en,

	&mst_e_sclk_pre_en,

	&mst_f_sclk_pre_en,

	&mst_a_sclk_div,

	&mst_b_sclk_div,

	&mst_c_sclk_div,

	&mst_d_sclk_div,

	&mst_e_sclk_div,

	&mst_f_sclk_div,

	&mst_a_sclk_post_en,

	&mst_b_sclk_post_en,

	&mst_c_sclk_post_en,

	&mst_d_sclk_post_en,

	&mst_e_sclk_post_en,

	&mst_f_sclk_post_en,

	&mst_a_sclk,

	&mst_b_sclk,

	&mst_c_sclk,

	&mst_d_sclk,

	&mst_e_sclk,

	&mst_f_sclk,

	&mst_a_lrclk_div,

	&mst_b_lrclk_div,

	&mst_c_lrclk_div,

	&mst_d_lrclk_div,

	&mst_e_lrclk_div,

	&mst_f_lrclk_div,

	&mst_a_lrclk,

	&mst_b_lrclk,

	&mst_c_lrclk,

	&mst_d_lrclk,

	&mst_e_lrclk,

	&mst_f_lrclk,

	&tdmin_a_sclk_sel,

	&tdmin_b_sclk_sel,

	&tdmin_c_sclk_sel,

	&tdmin_lb_sclk_sel,

	&tdmout_a_sclk_sel,

	&tdmout_b_sclk_sel,

	&tdmout_c_sclk_sel,

	&tdmin_a_sclk_pre_en,

	&tdmin_b_sclk_pre_en,

	&tdmin_c_sclk_pre_en,

	&tdmin_lb_sclk_pre_en,

	&tdmout_a_sclk_pre_en,

	&tdmout_b_sclk_pre_en,

	&tdmout_c_sclk_pre_en,

	&tdmin_a_sclk_post_en,

	&tdmin_b_sclk_post_en,

	&tdmin_c_sclk_post_en,

	&tdmin_lb_sclk_post_en,

	&tdmout_a_sclk_post_en,

	&tdmout_b_sclk_post_en,

	&tdmout_c_sclk_post_en,

	&tdmin_a_sclk,

	&tdmin_b_sclk,

	&tdmin_c_sclk,

	&tdmin_lb_sclk,

	&g12a_tdmout_a_sclk,

	&g12a_tdmout_b_sclk,

	&g12a_tdmout_c_sclk,

	&tdmin_a_lrclk,

	&tdmin_b_lrclk,

	&tdmin_c_lrclk,

	&tdmin_lb_lrclk,

	&tdmout_a_lrclk,

	&tdmout_b_lrclk,

	&tdmout_c_lrclk,

	&spdifout_b_clk_sel,

	&spdifout_b_clk_div,

	&spdifout_b_clk,

	&sm1_tdm_mclk_pad_0,

	&sm1_tdm_mclk_pad_1,

	&sm1_tdm_lrclk_pad_0,

	&sm1_tdm_lrclk_pad_1,

	&sm1_tdm_lrclk_pad_2,

	&sm1_tdm_sclk_pad_0,

	&sm1_tdm_sclk_pad_1,

	&sm1_tdm_sclk_pad_2,

	&sm1_aud_top,

	&toram,

	&eqdrc,

	&resample_b,

	&tovad,

	&locker,

	&spdifin_lb,

	&frddr_d,

	&toddr_d,

	&loopback_b,

	&sm1_clk81_en,

	&sm1_sysclk_a_div,

	&sm1_sysclk_a_en,

	&sm1_sysclk_b_div,

	&sm1_sysclk_b_en,

	&earcrx,

	&sm1_earcrx_cmdc_clk_sel,

	&sm1_earcrx_cmdc_clk_div,

	&sm1_earcrx_cmdc_clk,

	&sm1_earcrx_dmac_clk_sel,

	&sm1_earcrx_dmac_clk_div,

	&sm1_earcrx_dmac_clk,

};



static struct regmap_config axg_audio_regmap_cfg = {

	.reg_bits	= 32,

	.val_bits	= 32,
@@ -1739,8 +1318,6 @@ static struct regmap_config axg_audio_regmap_cfg = { 
};



struct audioclk_data {

	struct clk_regmap *const *regmap_clks;

	unsigned int regmap_clk_num;

	struct meson_clk_hw_data hw_clks;

	const char *rst_drvname;

	unsigned int max_register;
@@ -1783,10 +1360,6 @@ static int axg_audio_clkc_probe(struct platform_device *pdev) 
		return ret;

	}



	/* Populate regmap for the regmap backed clocks */

	for (i = 0; i < data->regmap_clk_num; i++)

		data->regmap_clks[i]->map = map;



	/* Take care to skip the registered input clocks */

	for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) {

		const char *name;
@@ -1821,8 +1394,6 @@ static int axg_audio_clkc_probe(struct platform_device *pdev) 
}



static const struct audioclk_data axg_audioclk_data = {

	.regmap_clks = axg_clk_regmaps,

	.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),

	.hw_clks = {

		.hws = axg_audio_hw_clks,

		.num = ARRAY_SIZE(axg_audio_hw_clks),
@@ -1831,8 +1402,6 @@ static const struct audioclk_data axg_audioclk_data = { 
};



static const struct audioclk_data g12a_audioclk_data = {

	.regmap_clks = g12a_clk_regmaps,

	.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),

	.hw_clks = {

		.hws = g12a_audio_hw_clks,

		.num = ARRAY_SIZE(g12a_audio_hw_clks),
@@ -1842,8 +1411,6 @@ static const struct audioclk_data g12a_audioclk_data = { 
};



static const struct audioclk_data sm1_audioclk_data = {

	.regmap_clks = sm1_clk_regmaps,

	.regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),

	.hw_clks = {

		.hws = sm1_audio_hw_clks,

		.num = ARRAY_SIZE(sm1_audio_hw_clks),

drivers/clk/meson/axg.c

+0 −131
Original line number Diff line number Diff line
@@ -2110,138 +2110,7 @@ static struct clk_hw *axg_hw_clks[] = { 
	[CLKID_VDIN_MEAS]		= &axg_vdin_meas.hw,

};



/* Convenience table to populate regmap in .probe */

static struct clk_regmap *const axg_clk_regmaps[] = {

	&axg_clk81,

	&axg_ddr,

	&axg_audio_locker,

	&axg_mipi_dsi_host,

	&axg_isa,

	&axg_pl301,

	&axg_periphs,

	&axg_spicc_0,

	&axg_i2c,

	&axg_rng0,

	&axg_uart0,

	&axg_mipi_dsi_phy,

	&axg_spicc_1,

	&axg_pcie_a,

	&axg_pcie_b,

	&axg_hiu_reg,

	&axg_assist_misc,

	&axg_emmc_b,

	&axg_emmc_c,

	&axg_dma,

	&axg_spi,

	&axg_audio,

	&axg_eth_core,

	&axg_uart1,

	&axg_g2d,

	&axg_usb0,

	&axg_usb1,

	&axg_reset,

	&axg_usb_general,

	&axg_ahb_arb0,

	&axg_efuse,

	&axg_boot_rom,

	&axg_ahb_data_bus,

	&axg_ahb_ctrl_bus,

	&axg_usb1_to_ddr,

	&axg_usb0_to_ddr,

	&axg_mmc_pclk,

	&axg_vpu_intr,

	&axg_sec_ahb_ahb3_bridge,

	&axg_gic,

	&axg_ao_media_cpu,

	&axg_ao_ahb_sram,

	&axg_ao_ahb_bus,

	&axg_ao_iface,

	&axg_ao_i2c,

	&axg_sd_emmc_b_clk0,

	&axg_sd_emmc_c_clk0,

	&axg_mpeg_clk_div,

	&axg_sd_emmc_b_clk0_div,

	&axg_sd_emmc_c_clk0_div,

	&axg_mpeg_clk_sel,

	&axg_sd_emmc_b_clk0_sel,

	&axg_sd_emmc_c_clk0_sel,

	&axg_mpll0,

	&axg_mpll1,

	&axg_mpll2,

	&axg_mpll3,

	&axg_mpll0_div,

	&axg_mpll1_div,

	&axg_mpll2_div,

	&axg_mpll3_div,

	&axg_fixed_pll,

	&axg_sys_pll,

	&axg_gp0_pll,

	&axg_hifi_pll,

	&axg_mpll_prediv,

	&axg_fclk_div2,

	&axg_fclk_div3,

	&axg_fclk_div4,

	&axg_fclk_div5,

	&axg_fclk_div7,

	&axg_pcie_pll_dco,

	&axg_pcie_pll_od,

	&axg_pcie_pll,

	&axg_pcie_mux,

	&axg_pcie_ref,

	&axg_pcie_cml_en0,

	&axg_pcie_cml_en1,

	&axg_gen_clk_sel,

	&axg_gen_clk_div,

	&axg_gen_clk,

	&axg_fixed_pll_dco,

	&axg_sys_pll_dco,

	&axg_gp0_pll_dco,

	&axg_hifi_pll_dco,

	&axg_pcie_pll_dco,

	&axg_pcie_pll_od,

	&axg_vpu_0_div,

	&axg_vpu_0_sel,

	&axg_vpu_0,

	&axg_vpu_1_div,

	&axg_vpu_1_sel,

	&axg_vpu_1,

	&axg_vpu,

	&axg_vapb_0_div,

	&axg_vapb_0_sel,

	&axg_vapb_0,

	&axg_vapb_1_div,

	&axg_vapb_1_sel,

	&axg_vapb_1,

	&axg_vapb_sel,

	&axg_vapb,

	&axg_vclk,

	&axg_vclk2,

	&axg_vclk_sel,

	&axg_vclk2_sel,

	&axg_vclk_input,

	&axg_vclk2_input,

	&axg_vclk_div,

	&axg_vclk_div1,

	&axg_vclk2_div,

	&axg_vclk2_div1,

	&axg_vclk_div2_en,

	&axg_vclk_div4_en,

	&axg_vclk_div6_en,

	&axg_vclk_div12_en,

	&axg_vclk2_div2_en,

	&axg_vclk2_div4_en,

	&axg_vclk2_div6_en,

	&axg_vclk2_div12_en,

	&axg_cts_encl_sel,

	&axg_cts_encl,

	&axg_vdin_meas_sel,

	&axg_vdin_meas_div,

	&axg_vdin_meas,

};



static const struct meson_eeclkc_data axg_clkc_data = {

	.regmap_clks = axg_clk_regmaps,

	.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),

	.hw_clks = {

		.hws = axg_hw_clks,

		.num = ARRAY_SIZE(axg_hw_clks),