Commit 4d695298 authored by Fabrizio Castro's avatar Fabrizio Castro Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a09g057: Add entries for the DMACs 



Add clock and reset entries for the Renesas RZ/V2H(P) DMAC IPs.

Signed-off-by: default avatarFabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250220150110.738619-2-fabrizio.castro.jz@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 9b12504e

drivers/clk/renesas/r9a09g057-cpg.c

+24 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ enum clk_ids { 
	CLK_PLLVDO,



	/* Internal Core Clocks */

	CLK_PLLCM33_DIV4,

	CLK_PLLCM33_DIV4_PLLCM33,

	CLK_PLLCM33_DIV16,

	CLK_PLLCLN_DIV2,

	CLK_PLLCLN_DIV8,
@@ -39,6 +41,8 @@ enum clk_ids { 
	CLK_PLLDTY_ACPU_DIV2,

	CLK_PLLDTY_ACPU_DIV4,

	CLK_PLLDTY_DIV16,

	CLK_PLLDTY_RCPU,

	CLK_PLLDTY_RCPU_DIV4,

	CLK_PLLVDO_CRU0,

	CLK_PLLVDO_CRU1,

	CLK_PLLVDO_CRU2,
@@ -85,6 +89,9 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 
	DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),



	/* Internal Core Clocks */

	DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),

	DEF_DDIV(".pllcm33_div4_pllcm33", CLK_PLLCM33_DIV4_PLLCM33,

		 CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),

	DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),



	DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
@@ -95,6 +102,8 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 
	DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),

	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),

	DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),

	DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),

	DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),



	DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),

	DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
@@ -115,6 +124,16 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 
};



static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {

	DEF_MOD("dmac_0_aclk",			CLK_PLLCM33_DIV4_PLLCM33, 0, 0, 0, 0,

						BUS_MSTOP(5, BIT(9))),

	DEF_MOD("dmac_1_aclk",			CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,

						BUS_MSTOP(3, BIT(2))),

	DEF_MOD("dmac_2_aclk",			CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2,

						BUS_MSTOP(3, BIT(3))),

	DEF_MOD("dmac_3_aclk",			CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3,

						BUS_MSTOP(10, BIT(11))),

	DEF_MOD("dmac_4_aclk",			CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4,

						BUS_MSTOP(10, BIT(12))),

	DEF_MOD_CRITICAL("icu_0_pclk_i",	CLK_PLLCM33_DIV16, 0, 5, 0, 5,

						BUS_MSTOP_NONE),

	DEF_MOD_CRITICAL("gic_0_gicclk",	CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
@@ -223,6 +242,11 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 


static const struct rzv2h_reset r9a09g057_resets[] __initconst = {

	DEF_RST(3, 0, 1, 1),		/* SYS_0_PRESETN */

	DEF_RST(3, 1, 1, 2),		/* DMAC_0_ARESETN */

	DEF_RST(3, 2, 1, 3),		/* DMAC_1_ARESETN */

	DEF_RST(3, 3, 1, 4),		/* DMAC_2_ARESETN */

	DEF_RST(3, 4, 1, 5),		/* DMAC_3_ARESETN */

	DEF_RST(3, 5, 1, 6),		/* DMAC_4_ARESETN */

	DEF_RST(3, 6, 1, 7),		/* ICU_0_PRESETN_I */

	DEF_RST(3, 8, 1, 9),		/* GIC_0_GICRESET_N */

	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */

drivers/clk/renesas/rzv2h-cpg.h

+2 −0
Original line number Diff line number Diff line
@@ -38,11 +38,13 @@ struct ddiv { 
#define CPG_CDDIV3		(0x40C)

#define CPG_CDDIV4		(0x410)



#define CDDIV0_DIVCTL1	DDIV_PACK(CPG_CDDIV0, 4, 3, 1)

#define CDDIV0_DIVCTL2	DDIV_PACK(CPG_CDDIV0, 8, 3, 2)

#define CDDIV1_DIVCTL0	DDIV_PACK(CPG_CDDIV1, 0, 2, 4)

#define CDDIV1_DIVCTL1	DDIV_PACK(CPG_CDDIV1, 4, 2, 5)

#define CDDIV1_DIVCTL2	DDIV_PACK(CPG_CDDIV1, 8, 2, 6)

#define CDDIV1_DIVCTL3	DDIV_PACK(CPG_CDDIV1, 12, 2, 7)

#define CDDIV3_DIVCTL2	DDIV_PACK(CPG_CDDIV3, 8, 3, 14)

#define CDDIV3_DIVCTL3	DDIV_PACK(CPG_CDDIV3, 12, 1, 15)

#define CDDIV4_DIVCTL0	DDIV_PACK(CPG_CDDIV4, 0, 1, 16)

#define CDDIV4_DIVCTL1	DDIV_PACK(CPG_CDDIV4, 4, 1, 17)