Commit 4d8aa430 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Jonathan Cameron
Browse files

dt-bindings: iio: adc: Add MediaTek MT6359 PMIC AUXADC 



Add a new binding for the MT6350 Series (MT6357/8/9) PMIC AUXADC,
providing various ADC channels for both internal temperatures and
voltages, audio accessory detection (hp/mic/hp+mic and buttons,
usually on a 3.5mm jack) other than some basic battery statistics
on boards where the battery is managed by this PMIC.

Also add the necessary dt-binding headers for devicetree consumers.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://patch.msgid.link/20240604123008.327424-2-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
parent 6dba0c39

Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/iio/adc/mediatek,mt6359-auxadc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek MT6350 series PMIC AUXADC



maintainers:

  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>



description:

  The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found

  in some MediaTek PMICs, performing various PMIC related measurements

  such as battery and PMIC internal voltage regulators temperatures,

  accessory detection resistance (usually, for a 3.5mm audio jack)

  other than voltages for various PMIC internal components.



properties:

  compatible:

    enum:

      - mediatek,mt6357-auxadc

      - mediatek,mt6358-auxadc

      - mediatek,mt6359-auxadc



  "#io-channel-cells":

    const: 1



required:

  - compatible

  - "#io-channel-cells"



additionalProperties: false

include/dt-bindings/iio/adc/mediatek,mt6357-auxadc.h

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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */



#ifndef _DT_BINDINGS_MEDIATEK_MT6357_AUXADC_H

#define _DT_BINDINGS_MEDIATEK_MT6357_AUXADC_H



/* ADC Channel Index */

#define MT6357_AUXADC_BATADC		0

#define MT6357_AUXADC_ISENSE		1

#define MT6357_AUXADC_VCDT		2

#define MT6357_AUXADC_BAT_TEMP		3

#define MT6357_AUXADC_CHIP_TEMP		4

#define MT6357_AUXADC_ACCDET		5

#define MT6357_AUXADC_VDCXO		6

#define MT6357_AUXADC_TSX_TEMP		7

#define MT6357_AUXADC_HPOFS_CAL		8

#define MT6357_AUXADC_DCXO_TEMP		9

#define MT6357_AUXADC_VCORE_TEMP	10

#define MT6357_AUXADC_VPROC_TEMP	11

#define MT6357_AUXADC_VBAT		12



#endif

include/dt-bindings/iio/adc/mediatek,mt6358-auxadc.h

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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */



#ifndef _DT_BINDINGS_MEDIATEK_MT6358_AUXADC_H

#define _DT_BINDINGS_MEDIATEK_MT6358_AUXADC_H



/* ADC Channel Index */

#define MT6358_AUXADC_BATADC		0

#define MT6358_AUXADC_VCDT		1

#define MT6358_AUXADC_BAT_TEMP		2

#define MT6358_AUXADC_CHIP_TEMP		3

#define MT6358_AUXADC_ACCDET		4

#define MT6358_AUXADC_VDCXO		5

#define MT6358_AUXADC_TSX_TEMP		6

#define MT6358_AUXADC_HPOFS_CAL		7

#define MT6358_AUXADC_DCXO_TEMP		8

#define MT6358_AUXADC_VBIF		9

#define MT6358_AUXADC_VCORE_TEMP	10

#define MT6358_AUXADC_VPROC_TEMP	11

#define MT6358_AUXADC_VGPU_TEMP		12

#define MT6358_AUXADC_VBAT		13



#endif

include/dt-bindings/iio/adc/mediatek,mt6359-auxadc.h

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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */



#ifndef _DT_BINDINGS_MEDIATEK_MT6359_AUXADC_H

#define _DT_BINDINGS_MEDIATEK_MT6359_AUXADC_H



/* ADC Channel Index */

#define MT6359_AUXADC_BATADC		0

#define MT6359_AUXADC_BAT_TEMP		1

#define MT6359_AUXADC_CHIP_TEMP		2

#define MT6359_AUXADC_ACCDET		3

#define MT6359_AUXADC_VDCXO		4

#define MT6359_AUXADC_TSX_TEMP		5

#define MT6359_AUXADC_HPOFS_CAL		6

#define MT6359_AUXADC_DCXO_TEMP		7

#define MT6359_AUXADC_VBIF		8

#define MT6359_AUXADC_VCORE_TEMP	9

#define MT6359_AUXADC_VPROC_TEMP	10

#define MT6359_AUXADC_VGPU_TEMP		11

#define MT6359_AUXADC_VBAT		12

#define MT6359_AUXADC_IBAT		13



#endif