dt-bindings: net: micrel: Convert to DT schema

Micrel PHY properties.

These properties cover the base properties Micrel PHYs.

Optional properties:

 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.

	Configure the LED mode with single value. The list of PHYs and the

	bits that are currently supported:

	KSZ8001: register 0x1e, bits 15..14

	KSZ8041: register 0x1e, bits 15..14

	KSZ8021: register 0x1f, bits 5..4

	KSZ8031: register 0x1f, bits 5..4

	KSZ8051: register 0x1f, bits 5..4

	KSZ8081: register 0x1f, bits 5..4

	KSZ8091: register 0x1f, bits 5..4

	LAN8814: register EP5.0, bit 6

	See the respective PHY datasheet for the mode values.

 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select

						bit selects 25 MHz mode

	Setting the RMII Reference Clock Select bit enables 25 MHz rather

	than 50 MHz clock mode.

	Note that this option is only needed for certain PHY revisions with a

	non-standard, inverted function of this configuration bit.

	Specifically, a clock reference ("rmii-ref" below) is always needed to

	actually select a mode.

 - clocks, clock-names: contains clocks according to the common clock bindings.

	supported clocks:

	- KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference

	  input clock. Used to determine the XI input clock.

 - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode

	Some PHYs, such as the KSZ8041FTL variant, support fiber mode, enabled

	by the FXEN boot strapping pin. It can't be determined from the PHY

	registers whether the PHY is in fiber mode, so this boolean device tree

	property can be used to describe it.

	In fiber mode, auto-negotiation is disabled and the PHY can only work in

	100base-fx (full and half duplex) modes.

 - coma-mode-gpios: If present the given gpio will be deasserted when the

		    PHY is probed.

	Some PHYs have a COMA mode input pin which puts the PHY into

	isolate and power-down mode. On some boards this input is connected

	to a GPIO of the SoC.

	Supported on the LAN8814.

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/net/micrel.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Micrel KSZ series PHYs and switches

maintainers:

  - Andrew Lunn <andrew@lunn.ch>

  - Stefan Eichenberger <eichest@gmail.com>

description:

  The Micrel KSZ series contains different network phys and switches.

properties:

  compatible:

    enum:

      - ethernet-phy-id000e.7237  # KSZ8873MLL

      - ethernet-phy-id0022.1430  # KSZ886X

      - ethernet-phy-id0022.1435  # KSZ8863

      - ethernet-phy-id0022.1510  # KSZ8041

      - ethernet-phy-id0022.1537  # KSZ8041RNLI

      - ethernet-phy-id0022.1550  # KSZ8051

      - ethernet-phy-id0022.1555  # KSZ8021

      - ethernet-phy-id0022.1556  # KSZ8031

      - ethernet-phy-id0022.1560  # KSZ8081, KSZ8091

      - ethernet-phy-id0022.1570  # KSZ8061

      - ethernet-phy-id0022.161a  # KSZ8001

      - ethernet-phy-id0022.1720  # KS8737

  micrel,fiber-mode:

    type: boolean

    description: |

      If present the PHY is configured to operate in fiber mode.

      The KSZ8041FTL variant supports fiber mode, enabled by the FXEN

      boot strapping pin. It can't be determined from the PHY registers

      whether the PHY is in fiber mode, so this boolean device tree

      property can be used to describe it.

      In fiber mode, auto-negotiation is disabled and the PHY can only

      work in 100base-fx (full and half duplex) modes.

  micrel,led-mode:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      LED mode value to set for PHYs with configurable LEDs.

      Configure the LED mode with single value. The list of PHYs and the

      bits that are currently supported:

      KSZ8001: register 0x1e, bits 15..14

      KSZ8041: register 0x1e, bits 15..14

      KSZ8021: register 0x1f, bits 5..4

      KSZ8031: register 0x1f, bits 5..4

      KSZ8051: register 0x1f, bits 5..4

      KSZ8081: register 0x1f, bits 5..4

      KSZ8091: register 0x1f, bits 5..4

      See the respective PHY datasheet for the mode values.

    minimum: 0

    maximum: 3

allOf:

  - $ref: ethernet-phy.yaml#

  - if:

      not:

        properties:

          compatible:

            contains:

              const: ethernet-phy-id0022.1510

    then:

      properties:

        micrel,fiber-mode: false

  - if:

      not:

        properties:

          compatible:

            contains:

              enum:

                - ethernet-phy-id0022.1510

                - ethernet-phy-id0022.1555

                - ethernet-phy-id0022.1556

                - ethernet-phy-id0022.1550

                - ethernet-phy-id0022.1560

                - ethernet-phy-id0022.161a

    then:

      properties:

        micrel,led-mode: false

  - if:

      properties:

        compatible:

          contains:

            enum:

              - ethernet-phy-id0022.1555

              - ethernet-phy-id0022.1556

              - ethernet-phy-id0022.1560

    then:

      properties:

        clock-names:

          const: rmii-ref

          description:

            The RMII reference input clock. Used to determine the XI input

            clock.

        micrel,rmii-reference-clock-select-25-mhz:

          type: boolean

          description: |

            RMII Reference Clock Select bit selects 25 MHz mode

            Setting the RMII Reference Clock Select bit enables 25 MHz rather

            than 50 MHz clock mode.

dependentRequired:

  micrel,rmii-reference-clock-select-25-mhz: [ clock-names ]

unevaluatedProperties: false

examples:

  - |

    mdio {

        #address-cells = <1>;

        #size-cells = <0>;

        ethernet-phy@5 {

            compatible = "ethernet-phy-id0022.1510";

            reg = <5>;

            micrel,led-mode = <2>;

            micrel,fiber-mode;

        };

    };