Commit 4e36f8ab authored by John Crispin's avatar John Crispin Committed by Bjorn Andersson
Browse files

clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support 



The CMN PLL in IPQ8074 SoC supplies fixed clocks to the networking
subsystem: bias_pll_cc_clk at 300 MHz and bias_pll_nss_noc_clk at
416.5 MHz.

Signed-off-by: default avatarJohn Crispin <john@phrozen.org>
Signed-off-by: default avatarChristian Marangi <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20260311183942.10134-5-ansuelsmth@gmail.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 7156c650

drivers/clk/qcom/ipq-cmn-pll.c

+8 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ 
#include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h>

#include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>

#include <dt-bindings/clock/qcom,ipq6018-cmn-pll.h>

#include <dt-bindings/clock/qcom,ipq8074-cmn-pll.h>



#define CMN_PLL_REFCLK_SRC_SELECTION		0x28

#define CMN_PLL_REFCLK_SRC_DIV			GENMASK(9, 8)
@@ -124,6 +125,12 @@ static const struct cmn_pll_fixed_output_clk ipq6018_output_clks[] = { 
	{ /* Sentinel */ }

};



static const struct cmn_pll_fixed_output_clk ipq8074_output_clks[] = {

	CLK_PLL_OUTPUT(IPQ8074_BIAS_PLL_CC_CLK, "bias_pll_cc_clk", 300000000UL),

	CLK_PLL_OUTPUT(IPQ8074_BIAS_PLL_NSS_NOC_CLK, "bias_pll_nss_noc_clk", 416500000UL),

	{ /* Sentinel */ }

};



static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = {

	CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),

	CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
@@ -456,6 +463,7 @@ static const struct of_device_id ipq_cmn_pll_clk_ids[] = { 
	{ .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks },

	{ .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks },

	{ .compatible = "qcom,ipq6018-cmn-pll", .data = &ipq6018_output_clks },

	{ .compatible = "qcom,ipq8074-cmn-pll", .data = &ipq8074_output_clks },

	{ .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks },

	{ }

};