Commit 4e6e93df authored by Khairul Anuar Romli's avatar Khairul Anuar Romli Committed by Dinh Nguyen
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arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node 



Move dma-controller node under simple-bus node to allow bus node specific
property able to be properly defined. This is require to fulfill Agilex5
bus limitation that is limited to 40-addressable-bit.

Update the compatible string for the DMA controller nodes in the Agilex5
device tree from the generic "snps,axi-dma-1.01a" to the platform-specific
"altr,agilex5-axi-dma". Add fallback capability to ensure driver is able
to initialize properly.

This change enables the use of platform-specific features and constraints
in the driver, such as setting a 40-bit DMA addressable mask through
dma-ranges, which is required for Agilex5. It also aligns with the updated
device tree bindings and driver support for this compatible string.

Signed-off-by: default avatarKhairul Anuar Romli <khairul.anuar.romli@altera.com>
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent e0f489a5

arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi

+43 −35
Original line number Diff line number Diff line
@@ -324,9 +324,17 @@ ocram: sram@0 { 
			#size-cells = <1>;

		};



		dmac0: dma-controller@10db0000 {

			compatible = "snps,axi-dma-1.01a";

			reg = <0x10db0000 0x500>;

		dma: dma-bus@10db0000 {

			compatible = "simple-bus";

			#address-cells = <1>;

			#size-cells = <2>;

			ranges = <0x00 0x10db0000 0x00 0x20000>;

			dma-ranges = <0x00 0x00 0x100 0x00>;



			dmac0: dma-controller@0 {

				compatible = "altr,agilex5-axi-dma",

					     "snps,axi-dma-1.01a";

				reg = <0x0 0x0 0x500>;

				clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,

					 <&clkmgr AGILEX5_L4_MP_CLK>;

				clock-names = "core-clk", "cfgr-clk";
@@ -340,12 +348,12 @@ dmac0: dma-controller@10db0000 { 
				snps,priority = <0 1 2 3>;

				snps,axi-max-burst-len = <8>;

				iommus = <&smmu 8>;

			dma-coherent;

			};



		dmac1: dma-controller@10dc0000 {

			compatible = "snps,axi-dma-1.01a";

			reg = <0x10dc0000 0x500>;

			dmac1: dma-controller@10000 {

				compatible = "altr,agilex5-axi-dma",

					     "snps,axi-dma-1.01a";

				reg = <0x10000 0x0 0x500>;

				clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,

					 <&clkmgr AGILEX5_L4_MP_CLK>;

				clock-names = "core-clk", "cfgr-clk";
@@ -359,7 +367,7 @@ dmac1: dma-controller@10dc0000 { 
				snps,priority = <0 1 2 3>;

				snps,axi-max-burst-len = <8>;

				iommus = <&smmu 9>;

			dma-coherent;

			};

		};



		rst: rstmgr@10d11000 {