Commit 4ebe2b8c authored by Arnaldo Carvalho de Melo's avatar Arnaldo Carvalho de Melo
Browse files

tools headers x86 cpufeatures: Sync with the kernel sources 



To pick the changes from:

  f24ef009 ("KVM: x86: Advertise MOVRS CPUID to userspace")
  f49ecf5e ("x86/cpufeature: Replace X86_FEATURE_SYSENTER32 with X86_FEATURE_SYSFAST32")
  db5e8249 ("KVM: SVM: Virtualize and advertise support for ERAPS")

This causes these perf files to be rebuilt and brings some X86_FEATURE
that may be used by:

      CC       /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o
      CC       /tmp/build/perf/bench/mem-memset-x86-64-asm.o

And addresses this perf build warning:

  Warning: Kernel ABI header differences:
    diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h

Please see tools/include/uapi/README for further details.

Cc: Amit Shah <amit.shah@amd.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Sean Christopherson <seanjc@google.com>
Cc: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 9cd28410

tools/arch/x86/include/asm/cpufeatures.h

+3 −1
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ 
#define X86_FEATURE_PEBS		( 3*32+12) /* "pebs" Precise-Event Based Sampling */

#define X86_FEATURE_BTS			( 3*32+13) /* "bts" Branch Trace Store */

#define X86_FEATURE_SYSCALL32		( 3*32+14) /* syscall in IA32 userspace */

#define X86_FEATURE_SYSENTER32		( 3*32+15) /* sysenter in IA32 userspace */

#define X86_FEATURE_SYSFAST32		( 3*32+15) /* sysenter/syscall in IA32 userspace */

#define X86_FEATURE_REP_GOOD		( 3*32+16) /* "rep_good" REP microcode works well */

#define X86_FEATURE_AMD_LBR_V2		( 3*32+17) /* "amd_lbr_v2" AMD Last Branch Record Extension Version 2 */

#define X86_FEATURE_CLEAR_CPU_BUF	( 3*32+18) /* Clear CPU buffers using VERW */
@@ -326,6 +326,7 @@ 
#define X86_FEATURE_AMX_FP16		(12*32+21) /* AMX fp16 Support */

#define X86_FEATURE_AVX_IFMA            (12*32+23) /* Support for VPMADD52[H,L]UQ */

#define X86_FEATURE_LAM			(12*32+26) /* "lam" Linear Address Masking */

#define X86_FEATURE_MOVRS		(12*32+31) /* MOVRS instructions */



/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */

#define X86_FEATURE_CLZERO		(13*32+ 0) /* "clzero" CLZERO instruction */
@@ -472,6 +473,7 @@ 
#define X86_FEATURE_GP_ON_USER_CPUID	(20*32+17) /* User CPUID faulting */



#define X86_FEATURE_PREFETCHI		(20*32+20) /* Prefetch Data/Instruction to Cache Level */

#define X86_FEATURE_ERAPS		(20*32+24) /* Enhanced Return Address Predictor Security */

#define X86_FEATURE_SBPB		(20*32+27) /* Selective Branch Prediction Barrier */

#define X86_FEATURE_IBPB_BRTYPE		(20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */

#define X86_FEATURE_SRSO_NO		(20*32+29) /* CPU is not affected by SRSO */