Commit 4eee627e authored by Lukasz Czechowski's avatar Lukasz Czechowski Committed by Heiko Stuebner
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arm64: dts: rockchip: Move uart5 pin configuration to px30 ringneck SoM 



In the PX30-uQ7 (Ringneck) SoM, the hardware CTS and RTS pins for
uart5 cannot be used for the UART CTS/RTS, because they are already
allocated for different purposes. CTS pin is routed to SUS_S3#
signal, while RTS pin is used internally and is not available on
Q7 connector. Move definition of the pinctrl-0 property from
px30-ringneck-haikou.dts to px30-ringneck.dtsi.

This commit is a dependency to next commit in the patch series,
that disables DMA for uart5.

Cc: stable@vger.kernel.org
Reviewed-by: default avatarQuentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: default avatarLukasz Czechowski <lukasz.czechowski@thaumatec.com>
Link: https://lore.kernel.org/r/20250121125604.3115235-2-lukasz.czechowski@thaumatec.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent a6a7cba1

arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts

+0 −1
Original line number Diff line number Diff line
@@ -226,7 +226,6 @@ &uart0 { 
};



&uart5 {

	pinctrl-0 = <&uart5_xfer>;

	rts-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;

	status = "okay";

};

arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -396,6 +396,10 @@ &u2phy_host { 
	status = "okay";

};



&uart5 {

	pinctrl-0 = <&uart5_xfer>;

};



/* Mule UCAN */

&usb_host0_ehci {

	status = "okay";