Commit 4faeef52 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: qcm2290: Add GPU nodes 



Describe the GPU hardware on the QCM2290.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-4-4bc0c19da4af@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent fcc6ed4f

arch/arm64/boot/dts/qcom/qcm2290.dtsi

+154 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>

#include <dt-bindings/clock/qcom,gcc-qcm2290.h>

#include <dt-bindings/clock/qcom,qcm2290-gpucc.h>

#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/dma/qcom-gpi.h>

#include <dt-bindings/firmware/qcom,scm.h>
@@ -758,6 +759,11 @@ qusb2_hstx_trim: hstx-trim@25b { 
				reg = <0x25b 0x1>;

				bits = <1 4>;

			};



			gpu_speed_bin: gpu-speed-bin@2006 {

				reg = <0x2006 0x2>;

				bits = <5 8>;

			};

		};



		pmu@1b8e300 {
@@ -1425,6 +1431,154 @@ usb_dwc3_ss: endpoint { 
			};

		};



		gpu: gpu@5900000 {

			compatible = "qcom,adreno-07000200", "qcom,adreno";

			reg = <0x0 0x05900000 0x0 0x40000>;

			reg-names = "kgsl_3d0_reg_memory";



			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,

				 <&gpucc GPU_CC_AHB_CLK>,

				 <&gcc GCC_BIMC_GPU_AXI_CLK>,

				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,

				 <&gpucc GPU_CC_CX_GMU_CLK>,

				 <&gpucc GPU_CC_CXO_CLK>;

			clock-names = "core",

				      "iface",

				      "mem_iface",

				      "alt_mem_iface",

				      "gmu",

				      "xo";



			interconnects = <&bimc MASTER_GFX3D RPM_ALWAYS_TAG

					 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;

			interconnect-names = "gfx-mem";



			iommus = <&adreno_smmu 0 1>,

				 <&adreno_smmu 2 0>;

			operating-points-v2 = <&gpu_opp_table>;

			power-domains = <&rpmpd QCM2290_VDDCX>;

			qcom,gmu = <&gmu_wrapper>;



			nvmem-cells = <&gpu_speed_bin>;

			nvmem-cell-names = "speed_bin";

			#cooling-cells = <2>;



			status = "disabled";



			zap-shader {

				memory-region = <&pil_gpu_mem>;

			};



			gpu_opp_table: opp-table {

				compatible = "operating-points-v2";



				/* TODO: Scale RPM_SMD_BIMC_GPU_CLK w/ turbo freqs */

				opp-1123200000 {

					opp-hz = /bits/ 64 <1123200000>;

					required-opps = <&rpmpd_opp_turbo_plus>;

					opp-peak-kBps = <6881000>;

					opp-supported-hw = <0x3>;

					turbo-mode;

				};



				opp-1017600000 {

					opp-hz = /bits/ 64 <1017600000>;

					required-opps = <&rpmpd_opp_turbo>;

					opp-peak-kBps = <6881000>;

					opp-supported-hw = <0x3>;

					turbo-mode;

				};



				opp-921600000 {

					opp-hz = /bits/ 64 <921600000>;

					required-opps = <&rpmpd_opp_nom_plus>;

					opp-peak-kBps = <6881000>;

					opp-supported-hw = <0x3>;

				};



				opp-844800000 {

					opp-hz = /bits/ 64 <844800000>;

					required-opps = <&rpmpd_opp_nom>;

					opp-peak-kBps = <6881000>;

					opp-supported-hw = <0x7>;

				};



				opp-672000000 {

					opp-hz = /bits/ 64 <672000000>;

					required-opps = <&rpmpd_opp_svs_plus>;

					opp-peak-kBps = <3879000>;

					opp-supported-hw = <0xf>;

				};



				opp-537600000 {

					opp-hz = /bits/ 64 <537600000>;

					required-opps = <&rpmpd_opp_svs>;

					opp-peak-kBps = <2929000>;

					opp-supported-hw = <0xf>;

				};



				opp-355200000 {

					opp-hz = /bits/ 64 <355200000>;

					required-opps = <&rpmpd_opp_low_svs>;

					opp-peak-kBps = <1720000>;

					opp-supported-hw = <0xf>;

				};

			};

		};



		gmu_wrapper: gmu@596a000 {

			compatible = "qcom,adreno-gmu-wrapper";

			reg = <0x0 0x0596a000 0x0 0x30000>;

			reg-names = "gmu";

			power-domains = <&gpucc GPU_CX_GDSC>,

					<&gpucc GPU_GX_GDSC>;

			power-domain-names = "cx",

					     "gx";

		};



		gpucc: clock-controller@5990000 {

			compatible = "qcom,qcm2290-gpucc";

			reg = <0x0 0x05990000 0x0 0x9000>;

			clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,

				 <&rpmcc RPM_SMD_XO_CLK_SRC>,

				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,

				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;

			power-domains = <&rpmpd QCM2290_VDDCX>;

			required-opps = <&rpmpd_opp_low_svs>;

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

		};



		adreno_smmu: iommu@59a0000 {

			compatible = "qcom,qcm2290-smmu-500", "qcom,adreno-smmu",

				     "qcom,smmu-500", "arm,mmu-500";

			reg = <0x0 0x059a0000 0x0 0x10000>;

			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,

				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,

				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;

			clock-names = "mem",

				      "hlos",

				      "iface";



			power-domains = <&gpucc GPU_CX_GDSC>;



			#global-interrupts = <1>;

			#iommu-cells = <2>;

		};



		mdss: display-subsystem@5e00000 {

			compatible = "qcom,qcm2290-mdss";

			reg = <0x0 0x05e00000 0x0 0x1000>;