crypto: ti - Add support for AES-XTS in DTHEv2 driver (4fbfd7b2) · Commits · git / linux-nf

drivers/crypto/ti/Kconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -6,6 +6,7 @@ config CRYPTO_DEV_TI_DTHEV2
		select CRYPTO_SKCIPHER
		select CRYPTO_ECB
		select CRYPTO_CBC
		select CRYPTO_XTS
		help
		This enables support for the TI DTHE V2 hw cryptography engine
		which can be found on TI K3 SOCs. Selecting this enables use

drivers/crypto/ti/dthev2-aes.c

+131 −6

Original line number	Diff line number	Diff line
		@@ -25,6 +25,7 @@

		// AES Engine
		#define DTHE_P_AES_BASE 0x7000

		#define DTHE_P_AES_KEY1_0 0x0038
		#define DTHE_P_AES_KEY1_1 0x003C
		#define DTHE_P_AES_KEY1_2 0x0030
		@@ -33,6 +34,16 @@
		#define DTHE_P_AES_KEY1_5 0x002C
		#define DTHE_P_AES_KEY1_6 0x0020
		#define DTHE_P_AES_KEY1_7 0x0024

		#define DTHE_P_AES_KEY2_0 0x0018
		#define DTHE_P_AES_KEY2_1 0x001C
		#define DTHE_P_AES_KEY2_2 0x0010
		#define DTHE_P_AES_KEY2_3 0x0014
		#define DTHE_P_AES_KEY2_4 0x0008
		#define DTHE_P_AES_KEY2_5 0x000C
		#define DTHE_P_AES_KEY2_6 0x0000
		#define DTHE_P_AES_KEY2_7 0x0004

		#define DTHE_P_AES_IV_IN_0 0x0040
		#define DTHE_P_AES_IV_IN_1 0x0044
		#define DTHE_P_AES_IV_IN_2 0x0048
		@@ -52,6 +63,7 @@
		enum aes_ctrl_mode_masks {
		AES_CTRL_ECB_MASK = 0x00,
		AES_CTRL_CBC_MASK = BIT(5),
		AES_CTRL_XTS_MASK = BIT(12) \| BIT(11),
		};

		#define DTHE_AES_CTRL_MODE_CLEAR_MASK ~GENMASK(28, 5)
		@@ -88,6 +100,31 @@ static int dthe_cipher_init_tfm(struct crypto_skcipher *tfm)
		return 0;
		}

		static int dthe_cipher_xts_init_tfm(struct crypto_skcipher *tfm)
		{
		struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);
		struct dthe_data *dev_data = dthe_get_dev(ctx);

		ctx->dev_data = dev_data;
		ctx->keylen = 0;

		ctx->skcipher_fb = crypto_alloc_sync_skcipher("xts(aes)", 0,
		CRYPTO_ALG_NEED_FALLBACK);
		if (IS_ERR(ctx->skcipher_fb)) {
		dev_err(dev_data->dev, "fallback driver xts(aes) couldn't be loaded\n");
		return PTR_ERR(ctx->skcipher_fb);
		}

		return 0;
		}

		static void dthe_cipher_xts_exit_tfm(struct crypto_skcipher *tfm)
		{
		struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);

		crypto_free_sync_skcipher(ctx->skcipher_fb);
		}

		static int dthe_aes_setkey(struct crypto_skcipher tfm, const u8 key, unsigned int keylen)
		{
		struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);
		@@ -119,6 +156,27 @@ static int dthe_aes_cbc_setkey(struct crypto_skcipher tfm, const u8 key, unsig
		return dthe_aes_setkey(tfm, key, keylen);
		}

		static int dthe_aes_xts_setkey(struct crypto_skcipher tfm, const u8 key, unsigned int keylen)
		{
		struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);

		if (keylen != 2 * AES_KEYSIZE_128 &&
		keylen != 2 * AES_KEYSIZE_192 &&
		keylen != 2 * AES_KEYSIZE_256)
		return -EINVAL;

		ctx->aes_mode = DTHE_AES_XTS;
		ctx->keylen = keylen / 2;
		memcpy(ctx->key, key, keylen);

		crypto_sync_skcipher_clear_flags(ctx->skcipher_fb, CRYPTO_TFM_REQ_MASK);
		crypto_sync_skcipher_set_flags(ctx->skcipher_fb,
		crypto_skcipher_get_flags(tfm) &
		CRYPTO_TFM_REQ_MASK);

		return crypto_sync_skcipher_setkey(ctx->skcipher_fb, key, keylen);
		}

		static void dthe_aes_set_ctrl_key(struct dthe_tfm_ctx *ctx,
		struct dthe_aes_req_ctx *rctx,
		u32 *iv_in)
		@@ -141,6 +199,24 @@ static void dthe_aes_set_ctrl_key(struct dthe_tfm_ctx *ctx,
		writel_relaxed(ctx->key[7], aes_base_reg + DTHE_P_AES_KEY1_7);
		}

		if (ctx->aes_mode == DTHE_AES_XTS) {
		size_t key2_offset = ctx->keylen / sizeof(u32);

		writel_relaxed(ctx->key[key2_offset + 0], aes_base_reg + DTHE_P_AES_KEY2_0);
		writel_relaxed(ctx->key[key2_offset + 1], aes_base_reg + DTHE_P_AES_KEY2_1);
		writel_relaxed(ctx->key[key2_offset + 2], aes_base_reg + DTHE_P_AES_KEY2_2);
		writel_relaxed(ctx->key[key2_offset + 3], aes_base_reg + DTHE_P_AES_KEY2_3);

		if (ctx->keylen > AES_KEYSIZE_128) {
		writel_relaxed(ctx->key[key2_offset + 4], aes_base_reg + DTHE_P_AES_KEY2_4);
		writel_relaxed(ctx->key[key2_offset + 5], aes_base_reg + DTHE_P_AES_KEY2_5);
		}
		if (ctx->keylen == AES_KEYSIZE_256) {
		writel_relaxed(ctx->key[key2_offset + 6], aes_base_reg + DTHE_P_AES_KEY2_6);
		writel_relaxed(ctx->key[key2_offset + 7], aes_base_reg + DTHE_P_AES_KEY2_7);
		}
		}

		if (rctx->enc)
		ctrl_val \|= DTHE_AES_CTRL_DIR_ENC;

		@@ -160,6 +236,9 @@ static void dthe_aes_set_ctrl_key(struct dthe_tfm_ctx *ctx,
		case DTHE_AES_CBC:
		ctrl_val \|= AES_CTRL_CBC_MASK;
		break;
		case DTHE_AES_XTS:
		ctrl_val \|= AES_CTRL_XTS_MASK;
		break;
		}

		if (iv_in) {
		@@ -315,24 +394,45 @@ static int dthe_aes_run(struct crypto_engine engine, void areq)
		local_bh_disable();
		crypto_finalize_skcipher_request(dev_data->engine, req, ret);
		local_bh_enable();
		return ret;
		return 0;
		}

		static int dthe_aes_crypt(struct skcipher_request *req)
		{
		struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
		struct dthe_aes_req_ctx *rctx = skcipher_request_ctx(req);
		struct dthe_data *dev_data = dthe_get_dev(ctx);
		struct crypto_engine *engine;

		/*
		* If data is not a multiple of AES_BLOCK_SIZE, need to return -EINVAL
		* If data length input is zero, no need to do any operation.
		* If data is not a multiple of AES_BLOCK_SIZE:
		* - need to return -EINVAL for ECB, CBC as they are block ciphers
		* - need to fallback to software as H/W doesn't support Ciphertext Stealing for XTS
		*/
		if (req->cryptlen % AES_BLOCK_SIZE)
		if (req->cryptlen % AES_BLOCK_SIZE) {
		if (ctx->aes_mode == DTHE_AES_XTS) {
		SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->skcipher_fb);

		skcipher_request_set_callback(subreq, skcipher_request_flags(req),
		req->base.complete, req->base.data);
		skcipher_request_set_crypt(subreq, req->src, req->dst,
		req->cryptlen, req->iv);

		return rctx->enc ? crypto_skcipher_encrypt(subreq) :
		crypto_skcipher_decrypt(subreq);
		}
		return -EINVAL;
		}

		if (req->cryptlen == 0)
		/*
		* If data length input is zero, no need to do any operation.
		* Except for XTS mode, where data length should be non-zero.
		*/
		if (req->cryptlen == 0) {
		if (ctx->aes_mode == DTHE_AES_XTS)
		return -EINVAL;
		return 0;
		}

		engine = dev_data->engine;
		return crypto_transfer_skcipher_request_to_engine(engine, req);
		@@ -399,7 +499,32 @@ static struct skcipher_engine_alg cipher_algs[] = {
		.cra_module = THIS_MODULE,
		},
		.op.do_one_request = dthe_aes_run,
		} /* CBC AES */
		}, /* CBC AES */
		{
		.base.init = dthe_cipher_xts_init_tfm,
		.base.exit = dthe_cipher_xts_exit_tfm,
		.base.setkey = dthe_aes_xts_setkey,
		.base.encrypt = dthe_aes_encrypt,
		.base.decrypt = dthe_aes_decrypt,
		.base.min_keysize = AES_MIN_KEY_SIZE * 2,
		.base.max_keysize = AES_MAX_KEY_SIZE * 2,
		.base.ivsize = AES_IV_SIZE,
		.base.base = {
		.cra_name = "xts(aes)",
		.cra_driver_name = "xts-aes-dthev2",
		.cra_priority = 299,
		.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER \|
		CRYPTO_ALG_ASYNC \|
		CRYPTO_ALG_KERN_DRIVER_ONLY \|
		CRYPTO_ALG_NEED_FALLBACK,
		.cra_alignmask = AES_BLOCK_SIZE - 1,
		.cra_blocksize = AES_BLOCK_SIZE,
		.cra_ctxsize = sizeof(struct dthe_tfm_ctx),
		.cra_reqsize = sizeof(struct dthe_aes_req_ctx),
		.cra_module = THIS_MODULE,
		},
		.op.do_one_request = dthe_aes_run,
		}, /* XTS AES */
		};

		int dthe_register_aes_algs(void)

drivers/crypto/ti/dthev2-common.h

+9 −1

Original line number	Diff line number	Diff line
		@@ -27,10 +27,16 @@

		#define DTHE_REG_SIZE 4
		#define DTHE_DMA_TIMEOUT_MS 2000
		/*
		* Size of largest possible key (of all algorithms) to be stored in dthe_tfm_ctx
		* This is currently the keysize of XTS-AES-256 which is 512 bits (64 bytes)
		*/
		#define DTHE_MAX_KEYSIZE (AES_MAX_KEY_SIZE * 2)

		enum dthe_aes_mode {
		DTHE_AES_ECB = 0,
		DTHE_AES_CBC,
		DTHE_AES_XTS,
		};

		/* Driver specific struct definitions */
		@@ -73,12 +79,14 @@ struct dthe_list {
		* @keylen: AES key length
		* @key: AES key
		* @aes_mode: AES mode
		* @skcipher_fb: Fallback crypto skcipher handle for AES-XTS mode
		*/
		struct dthe_tfm_ctx {
		struct dthe_data *dev_data;
		unsigned int keylen;
		u32 key[AES_KEYSIZE_256 / sizeof(u32)];
		u32 key[DTHE_MAX_KEYSIZE / sizeof(u32)];
		enum dthe_aes_mode aes_mode;
		struct crypto_sync_skcipher *skcipher_fb;
		};

		/**