Unverified Commit 50791f5d authored by Jernej Skrabec's avatar Jernej Skrabec Committed by Maxime Ripard
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drm/sun4i: tcon: set sync polarity for tcon1 channel 



Channel 1 has polarity bits for vsync and hsync signals but driver never
sets them. It turns out that with pre-HDMI2 controllers seemingly there
is no issue if polarity is not set. However, with HDMI2 controllers
(H6) there often comes to de-synchronization due to phase shift. This
causes flickering screen. It's safe to assume that similar issues might
happen also with pre-HDMI2 controllers.

Solve issue with setting vsync and hsync polarity. Note that display
stacks with tcon top have polarity bits actually in tcon0 polarity
register.

Fixes: 9026e0d1 ("drm: Add Allwinner A10 Display Engine support")
Reviewed-by: default avatarChen-Yu Tsai <wens@csie.org>
Tested-by: default avatarAndre Heider <a.heider@gmail.com>
Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20210209175900.7092-3-jernej.skrabec@siol.net
parent 873e5bb9

drivers/gpu/drm/sun4i/sun4i_tcon.c

+25 −0
Original line number Diff line number Diff line
@@ -689,6 +689,30 @@ static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, 
		     SUN4I_TCON1_BASIC5_V_SYNC(vsync) |

		     SUN4I_TCON1_BASIC5_H_SYNC(hsync));



	/* Setup the polarity of multiple signals */

	if (tcon->quirks->polarity_in_ch0) {

		val = 0;



		if (mode->flags & DRM_MODE_FLAG_PHSYNC)

			val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;



		if (mode->flags & DRM_MODE_FLAG_PVSYNC)

			val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;



		regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);

	} else {

		/* according to vendor driver, this bit must be always set */

		val = SUN4I_TCON1_IO_POL_UNKNOWN;



		if (mode->flags & DRM_MODE_FLAG_PHSYNC)

			val |= SUN4I_TCON1_IO_POL_HSYNC_POSITIVE;



		if (mode->flags & DRM_MODE_FLAG_PVSYNC)

			val |= SUN4I_TCON1_IO_POL_VSYNC_POSITIVE;



		regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val);

	}



	/* Map output pins to channel 1 */

	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,

			   SUN4I_TCON_GCTL_IOMAP_MASK,
@@ -1517,6 +1541,7 @@ static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = { 


static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = {

	.has_channel_1		= true,

	.polarity_in_ch0	= true,

	.set_mux		= sun8i_r40_tcon_tv_set_mux,

};

drivers/gpu/drm/sun4i/sun4i_tcon.h

+6 −0
Original line number Diff line number Diff line
@@ -153,6 +153,11 @@ 
#define SUN4I_TCON1_BASIC5_V_SYNC(height)		(((height) - 1) & 0x3ff)



#define SUN4I_TCON1_IO_POL_REG			0xf0

/* there is no documentation about this bit */

#define SUN4I_TCON1_IO_POL_UNKNOWN			BIT(26)

#define SUN4I_TCON1_IO_POL_HSYNC_POSITIVE		BIT(25)

#define SUN4I_TCON1_IO_POL_VSYNC_POSITIVE		BIT(24)



#define SUN4I_TCON1_IO_TRI_REG			0xf4



#define SUN4I_TCON_ECC_FIFO_REG			0xf8
@@ -235,6 +240,7 @@ struct sun4i_tcon_quirks { 
	bool	needs_de_be_mux; /* sun6i needs mux to select backend */

	bool    needs_edp_reset; /* a80 edp reset needed for tcon0 access */

	bool	supports_lvds;   /* Does the TCON support an LVDS output? */

	bool	polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */

	u8	dclk_min_div;	/* minimum divider for TCON0 DCLK */



	/* callback to handle tcon muxing options */