Commit 50cb7cca authored by Jeff Johnson's avatar Jeff Johnson
Browse files

wifi: ath11k: Correctly use "ab" macro parameter 

The checkpatch script is reporting multiple instances of:
	Argument 'x' is not used in function-like macro

Fix these by renaming the argument to match the usage. In the process,
also add parenthesis to the usage to avoid MACRO_ARG_PRECEDENCE
issues.

Compile tested only.

Link: https://patch.msgid.link/20251022-ath11k-bad-macro-arg-v1-1-93a8eadb6191@oss.qualcomm.com


Signed-off-by: default avatarJeff Johnson <jeff.johnson@oss.qualcomm.com>
parent 998c68e9

drivers/net/wireless/ath/ath11k/hal.h

+19 −19
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: BSD-3-Clause-Clear */

/*

 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.

 * Copyright (c) 2021-2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.

 */



#ifndef ATH11K_HAL_H
@@ -43,14 +43,14 @@ struct ath11k_base; 
#define HAL_SEQ_WCSS_UMAC_OFFSET		0x00a00000

#define HAL_SEQ_WCSS_UMAC_REO_REG		0x00a38000

#define HAL_SEQ_WCSS_UMAC_TCL_REG		0x00a44000

#define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(x) \

		(ab->hw_params.regs->hal_seq_wcss_umac_ce0_src_reg)

#define HAL_SEQ_WCSS_UMAC_CE0_DST_REG(x) \

		(ab->hw_params.regs->hal_seq_wcss_umac_ce0_dst_reg)

#define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(x) \

		(ab->hw_params.regs->hal_seq_wcss_umac_ce1_src_reg)

#define HAL_SEQ_WCSS_UMAC_CE1_DST_REG(x) \

		(ab->hw_params.regs->hal_seq_wcss_umac_ce1_dst_reg)

#define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) \

		((ab)->hw_params.regs->hal_seq_wcss_umac_ce0_src_reg)

#define HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) \

		((ab)->hw_params.regs->hal_seq_wcss_umac_ce0_dst_reg)

#define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) \

		((ab)->hw_params.regs->hal_seq_wcss_umac_ce1_src_reg)

#define HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) \

		((ab)->hw_params.regs->hal_seq_wcss_umac_ce1_dst_reg)

#define HAL_SEQ_WCSS_UMAC_WBM_REG		0x00a34000



#define HAL_CE_WFSS_CE_REG_BASE			0x01b80000
@@ -209,10 +209,10 @@ struct ath11k_base; 
#define HAL_REO_STATUS_HP(ab)			ab->hw_params.regs->hal_reo_status_hp



/* WBM Idle R0 address */

#define HAL_WBM_IDLE_LINK_RING_BASE_LSB(x) \

		(ab->hw_params.regs->hal_wbm_idle_link_ring_base_lsb)

#define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(x) \

		(ab->hw_params.regs->hal_wbm_idle_link_ring_misc)

#define HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab) \

		((ab)->hw_params.regs->hal_wbm_idle_link_ring_base_lsb)

#define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(ab) \

		((ab)->hw_params.regs->hal_wbm_idle_link_ring_misc)

#define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR	0x00000048

#define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR		0x0000004c

#define HAL_WBM_SCATTERED_RING_BASE_LSB		0x00000058
@@ -227,17 +227,17 @@ struct ath11k_base; 
#define HAL_WBM_IDLE_LINK_RING_HP		0x000030b0



/* SW2WBM R0 release address */

#define HAL_WBM_RELEASE_RING_BASE_LSB(x) \

		(ab->hw_params.regs->hal_wbm_release_ring_base_lsb)

#define HAL_WBM_RELEASE_RING_BASE_LSB(ab) \

		((ab)->hw_params.regs->hal_wbm_release_ring_base_lsb)



/* SW2WBM R2 release address */

#define HAL_WBM_RELEASE_RING_HP			0x00003018



/* WBM2SW R0 release address */

#define HAL_WBM0_RELEASE_RING_BASE_LSB(x) \

		(ab->hw_params.regs->hal_wbm0_release_ring_base_lsb)

#define HAL_WBM1_RELEASE_RING_BASE_LSB(x) \

		(ab->hw_params.regs->hal_wbm1_release_ring_base_lsb)

#define HAL_WBM0_RELEASE_RING_BASE_LSB(ab) \

		((ab)->hw_params.regs->hal_wbm0_release_ring_base_lsb)

#define HAL_WBM1_RELEASE_RING_BASE_LSB(ab) \

		((ab)->hw_params.regs->hal_wbm1_release_ring_base_lsb)



/* WBM2SW R2 release address */

#define HAL_WBM0_RELEASE_RING_HP		0x000030c0

drivers/net/wireless/ath/ath11k/pci.h

+9 −9
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: BSD-3-Clause-Clear */

/*

 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.

 * Copyright (c) 2021-2022,2024 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.

 */

#ifndef _ATH11K_PCI_H

#define _ATH11K_PCI_H
@@ -35,18 +35,18 @@ 
#define PCIE_SMLH_REQ_RST_LINK_DOWN		0x2

#define PCIE_INT_CLEAR_ALL			0xffffffff



#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(x) \

		(ab->hw_params.regs->pcie_qserdes_sysclk_en_sel)

#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab) \

		((ab)->hw_params.regs->pcie_qserdes_sysclk_en_sel)

#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL	0x10

#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK	0xffffffff

#define PCIE_PCS_OSC_DTCT_CONFIG1_REG(x) \

		(ab->hw_params.regs->pcie_pcs_osc_dtct_config_base)

#define PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab) \

		((ab)->hw_params.regs->pcie_pcs_osc_dtct_config_base)

#define PCIE_PCS_OSC_DTCT_CONFIG1_VAL		0x02

#define PCIE_PCS_OSC_DTCT_CONFIG2_REG(x) \

		(ab->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0x4)

#define PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab) \

		((ab)->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0x4)

#define PCIE_PCS_OSC_DTCT_CONFIG2_VAL		0x52

#define PCIE_PCS_OSC_DTCT_CONFIG4_REG(x) \

		(ab->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0xc)

#define PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab) \

		((ab)->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0xc)

#define PCIE_PCS_OSC_DTCT_CONFIG4_VAL		0xff

#define PCIE_PCS_OSC_DTCT_CONFIG_MSK		0x000000ff