Commit 5125fdc3 authored by Siddharth Vadapalli's avatar Siddharth Vadapalli Committed by Bjorn Helgaas
Browse files

PCI: keystone: Relocate ks_pcie_set/clear_dbi_mode() 

Relocate ks_pcie_set_dbi_mode() and ks_pcie_clear_dbi_mode() to avoid
forward declaration in a subsequent patch. No functional change intended.

Link: https://lore.kernel.org/linux-pci/20240328085041.2916899-2-s-vadapalli@ti.com


Signed-off-by: default avatarSiddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 1613e604

drivers/pci/controller/dwc/pci-keystone.c

+42 −42
Original line number Diff line number Diff line
@@ -245,6 +245,48 @@ static struct irq_chip ks_pcie_msi_irq_chip = { 
	.irq_unmask = ks_pcie_msi_unmask,

};



/**

 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers

 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone

 *	     PCIe host controller driver information.

 *

 * Since modification of dbi_cs2 involves different clock domain, read the

 * status back to ensure the transition is complete.

 */

static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)

{

	u32 val;



	val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	val |= DBI_CS2;

	ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);



	do {

		val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	} while (!(val & DBI_CS2));

}



/**

 * ks_pcie_clear_dbi_mode() - Disable DBI mode

 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone

 *	     PCIe host controller driver information.

 *

 * Since modification of dbi_cs2 involves different clock domain, read the

 * status back to ensure the transition is complete.

 */

static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)

{

	u32 val;



	val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	val &= ~DBI_CS2;

	ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);



	do {

		val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	} while (val & DBI_CS2);

}



static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp)

{

	pp->msi_irq_chip = &ks_pcie_msi_irq_chip;
@@ -340,48 +382,6 @@ static const struct irq_domain_ops ks_pcie_intx_irq_domain_ops = { 
	.xlate = irq_domain_xlate_onetwocell,

};



/**

 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers

 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone

 *	     PCIe host controller driver information.

 *

 * Since modification of dbi_cs2 involves different clock domain, read the

 * status back to ensure the transition is complete.

 */

static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)

{

	u32 val;



	val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	val |= DBI_CS2;

	ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);



	do {

		val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	} while (!(val & DBI_CS2));

}



/**

 * ks_pcie_clear_dbi_mode() - Disable DBI mode

 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone

 *	     PCIe host controller driver information.

 *

 * Since modification of dbi_cs2 involves different clock domain, read the

 * status back to ensure the transition is complete.

 */

static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)

{

	u32 val;



	val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	val &= ~DBI_CS2;

	ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);



	do {

		val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	} while (val & DBI_CS2);

}



static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)

{

	u32 val;