Commit 5208e7ce authored by Doug Brown's avatar Doug Brown Committed by Greg Kroah-Hartman
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serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level 



The FIFO is 64 bytes, but the FCR is configured to fire the TX interrupt
when the FIFO is half empty (bit 3 = 0). Thus, we should only write 32
bytes when a TX interrupt occurs.

This fixes a problem observed on the PXA168 that dropped a bunch of TX
bytes during large transmissions.

Fixes: ab28f51c ("serial: rewrite pxa2xx-uart to use 8250_core")
Signed-off-by: default avatarDoug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20240519191929.122202-1-doug@schmorgal.com


Cc: stable <stable@kernel.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 2c945120

drivers/tty/serial/8250/8250_pxa.c

+1 −0
Original line number Diff line number Diff line
@@ -125,6 +125,7 @@ static int serial_pxa_probe(struct platform_device *pdev) 
	uart.port.iotype = UPIO_MEM32;

	uart.port.regshift = 2;

	uart.port.fifosize = 64;

	uart.tx_loadsz = 32;

	uart.dl_write = serial_pxa_dl_write;



	ret = serial8250_register_8250_port(&uart);