Commit 52c4d1d6 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branch 'for-next/sysreg' into for-next/core 

* for-next/sysreg:
  : arm64 sysreg updates/cleanups
  arm64/sysreg: Remove unused define ARM64_FEATURE_FIELD_BITS
  KVM: arm64: selftests: Consider all 7 possible levels of cache
  KVM: arm64: selftests: Remove ARM64_FEATURE_FIELD_BITS and its last user
  arm64/sysreg: Add ICH_VMCR_EL2
  arm64/sysreg: Move generation of RES0/RES1/UNKN to function
  arm64/sysreg: Support feature-specific fields with 'Prefix' descriptor
  arm64/sysreg: Fix checks for incomplete sysreg definitions
  arm64/sysreg: Replace TCR_EL1 field macros
parents 17c05cb0 27abb1ee

arch/arm64/include/asm/assembler.h

+3 −3
Original line number Diff line number Diff line
@@ -325,14 +325,14 @@ alternative_cb_end 
 * tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map

 */

	.macro	tcr_set_t0sz, valreg, t0sz

	bfi	\valreg, \t0sz, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH

	bfi	\valreg, \t0sz, #TCR_EL1_T0SZ_SHIFT, #TCR_EL1_T0SZ_WIDTH

	.endm



/*

 * tcr_set_t1sz - update TCR.T1SZ

 */

	.macro	tcr_set_t1sz, valreg, t1sz

	bfi	\valreg, \t1sz, #TCR_T1SZ_OFFSET, #TCR_TxSZ_WIDTH

	bfi	\valreg, \t1sz, #TCR_EL1_T1SZ_SHIFT, #TCR_EL1_T1SZ_WIDTH

	.endm



/*
@@ -589,7 +589,7 @@ alternative_endif 
	.macro	offset_ttbr1, ttbr, tmp

#if defined(CONFIG_ARM64_VA_BITS_52) && !defined(CONFIG_ARM64_LPA2)

	mrs	\tmp, tcr_el1

	and	\tmp, \tmp, #TCR_T1SZ_MASK

	and	\tmp, \tmp, #TCR_EL1_T1SZ_MASK

	cmp	\tmp, #TCR_T1SZ(VA_BITS_MIN)

	orr	\tmp, \ttbr, #TTBR1_BADDR_4852_OFFSET

	csel	\ttbr, \tmp, \ttbr, eq

arch/arm64/include/asm/cputype.h

+1 −1
Original line number Diff line number Diff line
@@ -247,7 +247,7 @@ 
/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */

#define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX

#define MIDR_FUJITSU_ERRATUM_010001_MASK	(~MIDR_CPU_VAR_REV(1, 0))

#define TCR_CLEAR_FUJITSU_ERRATUM_010001	(TCR_NFD1 | TCR_NFD0)

#define TCR_CLEAR_FUJITSU_ERRATUM_010001	(TCR_EL1_NFD1 | TCR_EL1_NFD0)



#ifndef __ASSEMBLER__

arch/arm64/include/asm/mmu_context.h

+2 −2
Original line number Diff line number Diff line
@@ -68,10 +68,10 @@ static inline void __cpu_set_tcr_t0sz(unsigned long t0sz) 
{

	unsigned long tcr = read_sysreg(tcr_el1);



	if ((tcr & TCR_T0SZ_MASK) == t0sz)

	if ((tcr & TCR_EL1_T0SZ_MASK) == t0sz)

		return;



	tcr &= ~TCR_T0SZ_MASK;

	tcr &= ~TCR_EL1_T0SZ_MASK;

	tcr |= t0sz;

	write_sysreg(tcr, tcr_el1);

	isb();

arch/arm64/include/asm/pgtable-hwdef.h

+47 −96
Original line number Diff line number Diff line
@@ -228,102 +228,53 @@ 
/*

 * TCR flags.

 */

#define TCR_T0SZ_OFFSET		0

#define TCR_T1SZ_OFFSET		16

#define TCR_T0SZ(x)		((UL(64) - (x)) << TCR_T0SZ_OFFSET)

#define TCR_T1SZ(x)		((UL(64) - (x)) << TCR_T1SZ_OFFSET)

#define TCR_TxSZ(x)		(TCR_T0SZ(x) | TCR_T1SZ(x))

#define TCR_TxSZ_WIDTH		6

#define TCR_T0SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)

#define TCR_T1SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)



#define TCR_EPD0_SHIFT		7

#define TCR_EPD0_MASK		(UL(1) << TCR_EPD0_SHIFT)

#define TCR_IRGN0_SHIFT		8

#define TCR_IRGN0_MASK		(UL(3) << TCR_IRGN0_SHIFT)

#define TCR_IRGN0_NC		(UL(0) << TCR_IRGN0_SHIFT)

#define TCR_IRGN0_WBWA		(UL(1) << TCR_IRGN0_SHIFT)

#define TCR_IRGN0_WT		(UL(2) << TCR_IRGN0_SHIFT)

#define TCR_IRGN0_WBnWA		(UL(3) << TCR_IRGN0_SHIFT)



#define TCR_EPD1_SHIFT		23

#define TCR_EPD1_MASK		(UL(1) << TCR_EPD1_SHIFT)

#define TCR_IRGN1_SHIFT		24

#define TCR_IRGN1_MASK		(UL(3) << TCR_IRGN1_SHIFT)

#define TCR_IRGN1_NC		(UL(0) << TCR_IRGN1_SHIFT)

#define TCR_IRGN1_WBWA		(UL(1) << TCR_IRGN1_SHIFT)

#define TCR_IRGN1_WT		(UL(2) << TCR_IRGN1_SHIFT)

#define TCR_IRGN1_WBnWA		(UL(3) << TCR_IRGN1_SHIFT)



#define TCR_IRGN_NC		(TCR_IRGN0_NC | TCR_IRGN1_NC)

#define TCR_IRGN_WBWA		(TCR_IRGN0_WBWA | TCR_IRGN1_WBWA)

#define TCR_IRGN_WT		(TCR_IRGN0_WT | TCR_IRGN1_WT)

#define TCR_IRGN_WBnWA		(TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA)

#define TCR_IRGN_MASK		(TCR_IRGN0_MASK | TCR_IRGN1_MASK)





#define TCR_ORGN0_SHIFT		10

#define TCR_ORGN0_MASK		(UL(3) << TCR_ORGN0_SHIFT)

#define TCR_ORGN0_NC		(UL(0) << TCR_ORGN0_SHIFT)

#define TCR_ORGN0_WBWA		(UL(1) << TCR_ORGN0_SHIFT)

#define TCR_ORGN0_WT		(UL(2) << TCR_ORGN0_SHIFT)

#define TCR_ORGN0_WBnWA		(UL(3) << TCR_ORGN0_SHIFT)



#define TCR_ORGN1_SHIFT		26

#define TCR_ORGN1_MASK		(UL(3) << TCR_ORGN1_SHIFT)

#define TCR_ORGN1_NC		(UL(0) << TCR_ORGN1_SHIFT)

#define TCR_ORGN1_WBWA		(UL(1) << TCR_ORGN1_SHIFT)

#define TCR_ORGN1_WT		(UL(2) << TCR_ORGN1_SHIFT)

#define TCR_ORGN1_WBnWA		(UL(3) << TCR_ORGN1_SHIFT)



#define TCR_ORGN_NC		(TCR_ORGN0_NC | TCR_ORGN1_NC)

#define TCR_ORGN_WBWA		(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)

#define TCR_ORGN_WT		(TCR_ORGN0_WT | TCR_ORGN1_WT)

#define TCR_ORGN_WBnWA		(TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA)

#define TCR_ORGN_MASK		(TCR_ORGN0_MASK | TCR_ORGN1_MASK)



#define TCR_SH0_SHIFT		12

#define TCR_SH0_MASK		(UL(3) << TCR_SH0_SHIFT)

#define TCR_SH0_INNER		(UL(3) << TCR_SH0_SHIFT)



#define TCR_SH1_SHIFT		28

#define TCR_SH1_MASK		(UL(3) << TCR_SH1_SHIFT)

#define TCR_SH1_INNER		(UL(3) << TCR_SH1_SHIFT)

#define TCR_SHARED		(TCR_SH0_INNER | TCR_SH1_INNER)



#define TCR_TG0_SHIFT		14

#define TCR_TG0_MASK		(UL(3) << TCR_TG0_SHIFT)

#define TCR_TG0_4K		(UL(0) << TCR_TG0_SHIFT)

#define TCR_TG0_64K		(UL(1) << TCR_TG0_SHIFT)

#define TCR_TG0_16K		(UL(2) << TCR_TG0_SHIFT)



#define TCR_TG1_SHIFT		30

#define TCR_TG1_MASK		(UL(3) << TCR_TG1_SHIFT)

#define TCR_TG1_16K		(UL(1) << TCR_TG1_SHIFT)

#define TCR_TG1_4K		(UL(2) << TCR_TG1_SHIFT)

#define TCR_TG1_64K		(UL(3) << TCR_TG1_SHIFT)



#define TCR_IPS_SHIFT		32

#define TCR_IPS_MASK		(UL(7) << TCR_IPS_SHIFT)

#define TCR_A1			(UL(1) << 22)

#define TCR_ASID16		(UL(1) << 36)

#define TCR_TBI0		(UL(1) << 37)

#define TCR_TBI1		(UL(1) << 38)

#define TCR_HA			(UL(1) << 39)

#define TCR_HD			(UL(1) << 40)

#define TCR_HPD0_SHIFT		41

#define TCR_HPD0		(UL(1) << TCR_HPD0_SHIFT)

#define TCR_HPD1_SHIFT		42

#define TCR_HPD1		(UL(1) << TCR_HPD1_SHIFT)

#define TCR_TBID0		(UL(1) << 51)

#define TCR_TBID1		(UL(1) << 52)

#define TCR_NFD0		(UL(1) << 53)

#define TCR_NFD1		(UL(1) << 54)

#define TCR_E0PD0		(UL(1) << 55)

#define TCR_E0PD1		(UL(1) << 56)

#define TCR_TCMA0		(UL(1) << 57)

#define TCR_TCMA1		(UL(1) << 58)

#define TCR_DS			(UL(1) << 59)

#define TCR_T0SZ(x)		((UL(64) - (x)) << TCR_EL1_T0SZ_SHIFT)

#define TCR_T1SZ(x)		((UL(64) - (x)) << TCR_EL1_T1SZ_SHIFT)



#define TCR_T0SZ_MASK		TCR_EL1_T0SZ_MASK

#define TCR_T1SZ_MASK		TCR_EL1_T1SZ_MASK



#define TCR_EPD0_MASK		TCR_EL1_EPD0_MASK

#define TCR_EPD1_MASK		TCR_EL1_EPD1_MASK



#define TCR_IRGN0_MASK		TCR_EL1_IRGN0_MASK

#define TCR_IRGN0_WBWA		(TCR_EL1_IRGN0_WBWA << TCR_EL1_IRGN0_SHIFT)



#define TCR_ORGN0_MASK		TCR_EL1_ORGN0_MASK

#define TCR_ORGN0_WBWA		(TCR_EL1_ORGN0_WBWA << TCR_EL1_ORGN0_SHIFT)



#define TCR_SH0_MASK		TCR_EL1_SH0_MASK

#define TCR_SH0_INNER		(TCR_EL1_SH0_INNER << TCR_EL1_SH0_SHIFT)



#define TCR_SH1_MASK		TCR_EL1_SH1_MASK



#define TCR_TG0_SHIFT		TCR_EL1_TG0_SHIFT

#define TCR_TG0_MASK		TCR_EL1_TG0_MASK

#define TCR_TG0_4K		(TCR_EL1_TG0_4K << TCR_EL1_TG0_SHIFT)

#define TCR_TG0_64K		(TCR_EL1_TG0_64K << TCR_EL1_TG0_SHIFT)

#define TCR_TG0_16K		(TCR_EL1_TG0_16K << TCR_EL1_TG0_SHIFT)



#define TCR_TG1_SHIFT		TCR_EL1_TG1_SHIFT

#define TCR_TG1_MASK		TCR_EL1_TG1_MASK

#define TCR_TG1_16K		(TCR_EL1_TG1_16K << TCR_EL1_TG1_SHIFT)

#define TCR_TG1_4K		(TCR_EL1_TG1_4K << TCR_EL1_TG1_SHIFT)

#define TCR_TG1_64K		(TCR_EL1_TG1_64K << TCR_EL1_TG1_SHIFT)



#define TCR_IPS_SHIFT		TCR_EL1_IPS_SHIFT

#define TCR_IPS_MASK		TCR_EL1_IPS_MASK

#define TCR_A1			TCR_EL1_A1

#define TCR_ASID16		TCR_EL1_AS

#define TCR_TBI0		TCR_EL1_TBI0

#define TCR_TBI1		TCR_EL1_TBI1

#define TCR_HA			TCR_EL1_HA

#define TCR_HD			TCR_EL1_HD

#define TCR_HPD0		TCR_EL1_HPD0

#define TCR_HPD1		TCR_EL1_HPD1

#define TCR_TBID0		TCR_EL1_TBID0

#define TCR_TBID1		TCR_EL1_TBID1

#define TCR_E0PD0		TCR_EL1_E0PD0

#define TCR_E0PD1		TCR_EL1_E0PD1

#define TCR_DS			TCR_EL1_DS



/*

 * TTBR.

arch/arm64/include/asm/pgtable-prot.h

+1 −1
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ extern unsigned long prot_ns_shared; 
#else

static inline bool __pure lpa2_is_enabled(void)

{

	return read_tcr() & TCR_DS;

	return read_tcr() & TCR_EL1_DS;

}



#define PTE_MAYBE_SHARED	(lpa2_is_enabled() ? 0 : PTE_SHARED)