Commit 533140cb authored by Jani Nikula's avatar Jani Nikula Committed by Imre Deak
Browse files

drm/i915/dp: fix TGL and ICL max source rates 



Combo phy is limited to 5.4 GHz on low-voltage SKUs. Combo phy DP is
limited to 5.4 GHz, while combo phy eDP can do 8.1 GHz.

Bspec: 20584, 20598, 49180, 49201

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarAnimesh Manna <animesh.manna@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210901160402.24816-3-animesh.manna@intel.com
parent 6fd5a7c9

drivers/gpu/drm/i915/display/intel_dp.c

+10 −1
Original line number Diff line number Diff line
@@ -291,6 +291,15 @@ static int dg2_max_source_rate(struct intel_dp *intel_dp) 
	return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;

}



static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy)

{

	u32 voltage;



	voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & VOLTAGE_INFO_MASK;



	return voltage == VOLTAGE_INFO_0_85V;

}



static int icl_max_source_rate(struct intel_dp *intel_dp)

{

	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -298,7 +307,7 @@ static int icl_max_source_rate(struct intel_dp *intel_dp) 
	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);



	if (intel_phy_is_combo(dev_priv, phy) &&

	    !intel_dp_is_edp(intel_dp))

	    (is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp)))

		return 540000;



	return 810000;