Commit 5362e4d1 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Refresh meteorlake events 

Update the meteorlake events using the new tooling from:

  https://github.com/intel/perfmon



The events are unchanged but they are sorted and unused json values
are removed. This increases consistency across the json files. The
CPUID matching regular expression is updated to match the perfmon one.

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Acked-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-12-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 2c3fd22b

tools/perf/pmu-events/arch/x86/mapfile.csv

+1 −1
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ GenuineIntel-6-3A,v23,ivybridge,core 
GenuineIntel-6-3E,v22,ivytown,core

GenuineIntel-6-2D,v21,jaketown,core

GenuineIntel-6-(57|85),v9,knightslanding,core

GenuineIntel-6-AA,v1.00,meteorlake,core

GenuineIntel-6-A[AC],v1.00,meteorlake,core

GenuineIntel-6-1[AEF],v3,nehalemep,core

GenuineIntel-6-2E,v3,nehalemex,core

GenuineIntel-6-2A,v17,sandybridge,core

tools/perf/pmu-events/arch/x86/meteorlake/cache.json

+52 −118
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "L2 code requests",

        "EventCode": "0x24",

        "EventName": "L2_RQSTS.ALL_CODE_RD",

        "SampleAfterValue": "200003",

        "UMask": "0xe4",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Demand Data Read access L2 cache",

        "EventCode": "0x24",

        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",

        "SampleAfterValue": "200003",

        "UMask": "0xe1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.MISS",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "200003",

        "UMask": "0x41",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.MISS",

        "SampleAfterValue": "100003",

        "UMask": "0x41",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.REFERENCE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "200003",

        "UMask": "0x4f",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.REFERENCE",

        "SampleAfterValue": "100003",

        "UMask": "0x4f",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Retired load instructions.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_INST_RETIRED.ALL_LOADS",

        "PEBS": "1",

        "SampleAfterValue": "1000003",

        "UMask": "0x81",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Retired store instructions.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_INST_RETIRED.ALL_STORES",

        "PEBS": "1",

        "SampleAfterValue": "1000003",

        "UMask": "0x82",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts the number of load ops retired.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",

        "PEBS": "1",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "200003",

        "UMask": "0x81",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of store ops retired.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",

        "PEBS": "1",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "200003",

        "UMask": "0x82",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x80",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "TakenAlone": "1",

        "UMask": "0x5",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x10",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "TakenAlone": "1",

        "UMask": "0x5",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x100",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "TakenAlone": "1",

        "UMask": "0x5",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x20",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "TakenAlone": "1",

        "UMask": "0x5",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x4",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "TakenAlone": "1",

        "UMask": "0x5",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x200",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "TakenAlone": "1",

        "UMask": "0x5",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x40",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "TakenAlone": "1",

        "UMask": "0x5",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x8",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "TakenAlone": "1",

        "UMask": "0x5",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "UMask": "0x6",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "L2 code requests",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x24",

        "EventName": "L2_RQSTS.ALL_CODE_RD",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0xe4",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Demand Data Read access L2 cache",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x24",

        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0xe1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.MISS",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "UMask": "0x41",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.REFERENCE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "UMask": "0x4f",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Retired load instructions.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_INST_RETIRED.ALL_LOADS",

        "PEBS": "1",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "UMask": "0x81",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Retired store instructions.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_INST_RETIRED.ALL_STORES",

        "L1_Hit_Indication": "1",

        "PEBS": "1",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "UMask": "0x82",

        "Unit": "cpu_core"

    }

]

tools/perf/pmu-events/arch/x86/meteorlake/frontend.json

+0 −6
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x80",

        "EventName": "ICACHE.ACCESSES",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "200003",

        "UMask": "0x3",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x80",

        "EventName": "ICACHE.MISSES",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "200003",

        "UMask": "0x2",

        "Unit": "cpu_atom"

tools/perf/pmu-events/arch/x86/meteorlake/memory.json

+20 −57
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts cacheable demand data reads were not supplied by the L3 cache.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00002",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x80",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "1009",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x10",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "20011",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x100",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "503",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x20",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "100007",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x4",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x200",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "101",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x40",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "2003",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x8",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "50021",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",

        "CollectPEBSRecord": "2",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
@@ -160,9 +105,18 @@ 
        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts cacheable demand data reads were not supplied by the L3 cache.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",
@@ -171,9 +125,18 @@ 
        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00002",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

tools/perf/pmu-events/arch/x86/meteorlake/other.json

+10 −14
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts cacheable demand data reads Catch all value for any response types - this includes response types not define in the OCR.  If this is set all other response types will be ignored",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",
@@ -10,20 +9,8 @@ 
        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO Catch all value for any response types - this includes response types not define in the OCR.  If this is set all other response types will be ignored",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10002",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand data reads that have any type of response.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",
@@ -32,9 +19,18 @@ 
        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO Catch all value for any response types - this includes response types not define in the OCR.  If this is set all other response types will be ignored",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10002",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",