ARM: OMAP2+: Drop legacy platform data for dra7 l3 (53fb6ae9) · Commits · git / linux-nf

arch/arm/mach-omap2/omap_hwmod_7xx_data.c

+0 −162

Original line number	Diff line number	Diff line
		@@ -26,172 +26,10 @@
		/* Base offset for all DRA7XX interrupts external to MPUSS */
		#define DRA7XX_IRQ_GIC_START 32

		/*
		* IP blocks
		*/

		/*
		* 'l3' class
		* instance(s): l3_instr, l3_main_1, l3_main_2
		*/
		static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
		.name = "l3",
		};

		/* l3_instr */
		static struct omap_hwmod dra7xx_l3_instr_hwmod = {
		.name = "l3_instr",
		.class = &dra7xx_l3_hwmod_class,
		.clkdm_name = "l3instr_clkdm",
		.prcm = {
		.omap4 = {
		.clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
		.context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
		.modulemode = MODULEMODE_HWCTRL,
		},
		},
		};

		/* l3_main_1 */
		static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
		.name = "l3_main_1",
		.class = &dra7xx_l3_hwmod_class,
		.clkdm_name = "l3main1_clkdm",
		.prcm = {
		.omap4 = {
		.clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
		.context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
		},
		},
		};

		/* l3_main_2 */
		static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
		.name = "l3_main_2",
		.class = &dra7xx_l3_hwmod_class,
		.clkdm_name = "l3instr_clkdm",
		.prcm = {
		.omap4 = {
		.clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
		.context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
		.modulemode = MODULEMODE_HWCTRL,
		},
		},
		};

		/*
		* 'bb2d' class
		*
		*/

		static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
		.name = "bb2d",
		};

		/* bb2d */
		static struct omap_hwmod dra7xx_bb2d_hwmod = {
		.name = "bb2d",
		.class = &dra7xx_bb2d_hwmod_class,
		.clkdm_name = "dss_clkdm",
		.main_clk = "dpll_core_h24x2_ck",
		.prcm = {
		.omap4 = {
		.clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
		.context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
		.modulemode = MODULEMODE_SWCTRL,
		},
		},
		};

		/*
		* 'vcp' class
		*
		*/

		static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
		.name = "vcp",
		};

		/* vcp1 */
		static struct omap_hwmod dra7xx_vcp1_hwmod = {
		.name = "vcp1",
		.class = &dra7xx_vcp_hwmod_class,
		.clkdm_name = "l3main1_clkdm",
		.main_clk = "l3_iclk_div",
		.prcm = {
		.omap4 = {
		.clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
		.context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
		},
		},
		};

		/* vcp2 */
		static struct omap_hwmod dra7xx_vcp2_hwmod = {
		.name = "vcp2",
		.class = &dra7xx_vcp_hwmod_class,
		.clkdm_name = "l3main1_clkdm",
		.main_clk = "l3_iclk_div",
		.prcm = {
		.omap4 = {
		.clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
		.context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
		},
		},
		};



		/*
		* Interfaces
		*/

		/* l3_main_2 -> l3_instr */
		static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
		.master = &dra7xx_l3_main_2_hwmod,
		.slave = &dra7xx_l3_instr_hwmod,
		.clk = "l3_iclk_div",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l3_main_1 -> l3_main_2 */
		static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
		.master = &dra7xx_l3_main_1_hwmod,
		.slave = &dra7xx_l3_main_2_hwmod,
		.clk = "l3_iclk_div",
		.user = OCP_USER_MPU,
		};

		/* l3_main_1 -> bb2d */
		static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
		.master = &dra7xx_l3_main_1_hwmod,
		.slave = &dra7xx_bb2d_hwmod,
		.clk = "l3_iclk_div",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l3_main_1 -> vcp1 */
		static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
		.master = &dra7xx_l3_main_1_hwmod,
		.slave = &dra7xx_vcp1_hwmod,
		.clk = "l3_iclk_div",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l3_main_1 -> vcp2 */
		static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
		.master = &dra7xx_l3_main_1_hwmod,
		.slave = &dra7xx_vcp2_hwmod,
		.clk = "l3_iclk_div",
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
		&dra7xx_l3_main_2__l3_instr,
		&dra7xx_l3_main_1__l3_main_2,
		&dra7xx_l3_main_1__bb2d,
		&dra7xx_l3_main_1__vcp1,
		&dra7xx_l3_main_1__vcp2,
		NULL,
		};