Commit 54b3f0e6 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: remove last traces of I915_READ(), I915_WRITE() and POSTING_READ() 



Good riddance! Remove the macros and their remaining references in
comments.

The following functions should be used instead, depending on the use
case:

- intel_uncore_read(), intel_uncore_write(), intel_uncore_posting_read()

- intel_de_read(), intel_de_write(), intel_de_posting_read()

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201130111601.2817-10-jani.nikula@intel.com
parent f9c914a5

drivers/gpu/drm/i915/display/intel_dvo.c

+0 −4
Original line number Diff line number Diff line
@@ -301,12 +301,8 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state, 
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)

		dvo_val |= DVO_VSYNC_ACTIVE_HIGH;



	/*I915_WRITE(DVOB_SRCDIM,

	  (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |

	  (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/

	intel_de_write(dev_priv, dvo_srcdim_reg,

		       (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));

	/*I915_WRITE(DVOB, dvo_val);*/

	intel_de_write(dev_priv, dvo_reg, dvo_val);

}

drivers/gpu/drm/i915/i915_drv.h

+0 −8
Original line number Diff line number Diff line
@@ -1972,14 +1972,6 @@ mkwrite_device_info(struct drm_i915_private *dev_priv) 
int i915_reg_read_ioctl(struct drm_device *dev, void *data,

			struct drm_file *file);



#define __I915_REG_OP(op__, dev_priv__, ...) \

	intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)



#define I915_READ(reg__)	 __I915_REG_OP(read, dev_priv, (reg__))

#define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))



#define POSTING_READ(reg__)	__I915_REG_OP(posting_read, dev_priv, (reg__))



/* i915_mm.c */

int remap_io_mapping(struct vm_area_struct *vma,

		     unsigned long addr, unsigned long pfn, unsigned long size,

drivers/gpu/drm/i915/i915_reg.h

+4 −2
Original line number Diff line number Diff line
@@ -10853,8 +10853,10 @@ enum skl_power_gate { 
#define  CNL_DRAM_RANK_3			(0x2 << 9)

#define  CNL_DRAM_RANK_4			(0x3 << 9)



/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,

 * since on HSW we can't write to it using I915_WRITE. */

/*

 * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,

 * since on HSW we can't write to it using intel_uncore_write.

 */

#define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)

#define D_COMP_BDW			_MMIO(0x138144)

#define  D_COMP_RCOMP_IN_PROGRESS	(1 << 9)

drivers/gpu/drm/i915/intel_sideband.c

+2 −2
Original line number Diff line number Diff line
@@ -404,8 +404,8 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915, 
	lockdep_assert_held(&i915->sb_lock);



	/*

	 * GEN6_PCODE_* are outside of the forcewake domain, we can

	 * use te fw I915_READ variants to reduce the amount of work

	 * GEN6_PCODE_* are outside of the forcewake domain, we can use

	 * intel_uncore_read/write_fw variants to reduce the amount of work

	 * required when reading/writing.

	 */

drivers/gpu/drm/i915/intel_uncore.c

+1 −1
Original line number Diff line number Diff line
@@ -2126,7 +2126,7 @@ int __intel_wait_for_register_fw(struct intel_uncore *uncore, 
 * This routine waits until the target register @reg contains the expected

 * @value after applying the @mask, i.e. it waits until ::

 *

 *     (I915_READ(reg) & mask) == value

 *     (intel_uncore_read(uncore, reg) & mask) == value

 *

 * Otherwise, the wait will timeout after @timeout_ms milliseconds.

 *