Commit 553f973a authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
Browse files

drm/amd/amdgpu: Update debugfs for XCC support (v3) 



This patch updates the 'regs2' interface for MMIO
registers to add a new IOCTL command for a 'v2' state
data that includes the XCC ID.

This patch then updates amdgpu_gfx_select_se_sh()
and amdgpu_gfx_select_me_pipe_q() (and the implementations
in the gfx drivers) to support an additional parameter.

This patch then creates a new debugfs interface "gprwave"
which is a merge of shader GPR and wave status access.  This
new inteface uses an IOCTL to select banks as well as XCC identity.

(v2) Fix missing xcc_id in wave_ind function

(v3) Fix pm runtime calls and mutex locking

(v4) Fix bad label

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarHarish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5f09237b

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

+184 −18
Original line number Diff line number Diff line
@@ -139,7 +139,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f, 
					sh_bank, instance_bank, 0);

	} else if (use_ring) {

		mutex_lock(&adev->srbm_mutex);

		amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid);

		amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid, 0);

	}



	if (pm_pg_lock)
@@ -172,7 +172,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f, 
		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);

		mutex_unlock(&adev->grbm_idx_mutex);

	} else if (use_ring) {

		amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);

		amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0, 0);

		mutex_unlock(&adev->srbm_mutex);

	}
@@ -264,13 +264,13 @@ static ssize_t amdgpu_debugfs_regs2_op(struct file *f, char __user *buf, u32 off 
		mutex_lock(&adev->grbm_idx_mutex);

		amdgpu_gfx_select_se_sh(adev, rd->id.grbm.se,

						  rd->id.grbm.sh,

								rd->id.grbm.instance, 0);

						  rd->id.grbm.instance, rd->id.xcc_id);

	}



	if (rd->id.use_srbm) {

		mutex_lock(&adev->srbm_mutex);

		amdgpu_gfx_select_me_pipe_q(adev, rd->id.srbm.me, rd->id.srbm.pipe,

									rd->id.srbm.queue, rd->id.srbm.vmid);

					    rd->id.srbm.queue, rd->id.srbm.vmid, rd->id.xcc_id);

	}



	if (rd->id.pg_lock)
@@ -296,12 +296,12 @@ static ssize_t amdgpu_debugfs_regs2_op(struct file *f, char __user *buf, u32 off 
	}

end:

	if (rd->id.use_grbm) {

		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);

		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, rd->id.xcc_id);

		mutex_unlock(&adev->grbm_idx_mutex);

	}



	if (rd->id.use_srbm) {

		amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);

		amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0, rd->id.xcc_id);

		mutex_unlock(&adev->srbm_mutex);

	}
@@ -320,19 +320,45 @@ static ssize_t amdgpu_debugfs_regs2_op(struct file *f, char __user *buf, u32 off 
static long amdgpu_debugfs_regs2_ioctl(struct file *f, unsigned int cmd, unsigned long data)

{

	struct amdgpu_debugfs_regs2_data *rd = f->private_data;

	struct amdgpu_debugfs_regs2_iocdata v1_data;

	int r;



	switch (cmd) {

	case AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE:

	mutex_lock(&rd->lock);

		r = copy_from_user(&rd->id, (struct amdgpu_debugfs_regs2_iocdata *)data,



	switch (cmd) {

	case AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE_V2:

		r = copy_from_user(&rd->id, (struct amdgpu_debugfs_regs2_iocdata_v2 *)data,

				   sizeof(rd->id));

		mutex_unlock(&rd->lock);

		return r ? -EINVAL : 0;

	default:

		return -EINVAL;

		if (r)

			r = -EINVAL;

		goto done;

	case AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE:

		r = copy_from_user(&v1_data, (struct amdgpu_debugfs_regs2_iocdata *)data,

				   sizeof(v1_data));

		if (r) {

			r = -EINVAL;

			goto done;

		}

	return 0;

		goto v1_copy;

	default:

		r = -EINVAL;

		goto done;

	}



v1_copy:

	rd->id.use_srbm = v1_data.use_srbm;

	rd->id.use_grbm = v1_data.use_grbm;

	rd->id.pg_lock = v1_data.pg_lock;

	rd->id.grbm.se = v1_data.grbm.se;

	rd->id.grbm.sh = v1_data.grbm.sh;

	rd->id.grbm.instance = v1_data.grbm.instance;

	rd->id.srbm.me = v1_data.srbm.me;

	rd->id.srbm.pipe = v1_data.srbm.pipe;

	rd->id.srbm.queue = v1_data.srbm.queue;

	rd->id.xcc_id = 0;

done:

	mutex_unlock(&rd->lock);

	return r;

}



static ssize_t amdgpu_debugfs_regs2_read(struct file *f, char __user *buf, size_t size, loff_t *pos)
@@ -345,6 +371,135 @@ static ssize_t amdgpu_debugfs_regs2_write(struct file *f, const char __user *buf 
	return amdgpu_debugfs_regs2_op(f, (char __user *)buf, *pos, size, 1);

}



static int amdgpu_debugfs_gprwave_open(struct inode *inode, struct file *file)

{

	struct amdgpu_debugfs_gprwave_data *rd;



	rd = kzalloc(sizeof *rd, GFP_KERNEL);

	if (!rd)

		return -ENOMEM;

	rd->adev = file_inode(file)->i_private;

	file->private_data = rd;

	mutex_init(&rd->lock);



	return 0;

}



static int amdgpu_debugfs_gprwave_release(struct inode *inode, struct file *file)

{

	struct amdgpu_debugfs_gprwave_data *rd = file->private_data;

	mutex_destroy(&rd->lock);

	kfree(file->private_data);

	return 0;

}



static ssize_t amdgpu_debugfs_gprwave_read(struct file *f, char __user *buf, size_t size, loff_t *pos)

{

	struct amdgpu_debugfs_gprwave_data *rd = f->private_data;

	struct amdgpu_device *adev = rd->adev;

	ssize_t result = 0;

	int r;

	uint32_t *data, x;



	if (size & 0x3 || *pos & 0x3)

		return -EINVAL;



	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);

	if (r < 0) {

		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);

		return r;

	}



	r = amdgpu_virt_enable_access_debugfs(adev);

	if (r < 0) {

		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);

		return r;

	}



	data = kcalloc(1024, sizeof(*data), GFP_KERNEL);

	if (!data) {

		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);

		amdgpu_virt_disable_access_debugfs(adev);

		return -ENOMEM;

	}



	/* switch to the specific se/sh/cu */

	mutex_lock(&adev->grbm_idx_mutex);

	amdgpu_gfx_select_se_sh(adev, rd->id.se, rd->id.sh, rd->id.cu, rd->id.xcc_id);



	if (!rd->id.gpr_or_wave) {

		x = 0;

		if (adev->gfx.funcs->read_wave_data)

			adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x);

	} else {

		x = size >> 2;

		if (rd->id.gpr.vpgr_or_sgpr) {

			if (adev->gfx.funcs->read_wave_vgprs)

				adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread, *pos, size>>2, data);

		} else {

			if (adev->gfx.funcs->read_wave_sgprs)

				adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, data);

		}

	}



	amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, rd->id.xcc_id);

	mutex_unlock(&adev->grbm_idx_mutex);



	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);

	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);



	if (!x) {

		result = -EINVAL;

		goto done;

	}



	while (size && (*pos < x * 4)) {

		uint32_t value;



		value = data[*pos >> 2];

		r = put_user(value, (uint32_t *)buf);

		if (r) {

			result = r;

			goto done;

		}



		result += 4;

		buf += 4;

		*pos += 4;

		size -= 4;

	}



done:

	amdgpu_virt_disable_access_debugfs(adev);

	kfree(data);

	return result;

}



static long amdgpu_debugfs_gprwave_ioctl(struct file *f, unsigned int cmd, unsigned long data)

{

	struct amdgpu_debugfs_gprwave_data *rd = f->private_data;

	int r;



	mutex_lock(&rd->lock);



	switch (cmd) {

	case AMDGPU_DEBUGFS_GPRWAVE_IOC_SET_STATE:

		r = copy_from_user(&rd->id, (struct amdgpu_debugfs_gprwave_iocdata *)data, sizeof rd->id);

		if (r)

			return r ? -EINVAL : 0;

		goto done;

	default:

		r = -EINVAL;

		goto done;

	}



done:

	mutex_unlock(&rd->lock);

	return r;

}









/**

 * amdgpu_debugfs_regs_pcie_read - Read from a PCIE register
@@ -913,7 +1068,7 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, 


	x = 0;

	if (adev->gfx.funcs->read_wave_data)

		adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);

		adev->gfx.funcs->read_wave_data(adev, 0, simd, wave, data, &x);



	amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0);

	mutex_unlock(&adev->grbm_idx_mutex);
@@ -1007,10 +1162,10 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, 


	if (bank == 0) {

		if (adev->gfx.funcs->read_wave_vgprs)

			adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);

			adev->gfx.funcs->read_wave_vgprs(adev, 0, simd, wave, thread, offset, size>>2, data);

	} else {

		if (adev->gfx.funcs->read_wave_sgprs)

			adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);

			adev->gfx.funcs->read_wave_sgprs(adev, 0, simd, wave, offset, size>>2, data);

	}



	amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0);
@@ -1341,6 +1496,15 @@ static const struct file_operations amdgpu_debugfs_regs2_fops = { 
	.llseek = default_llseek

};



static const struct file_operations amdgpu_debugfs_gprwave_fops = {

	.owner = THIS_MODULE,

	.unlocked_ioctl = amdgpu_debugfs_gprwave_ioctl,

	.read = amdgpu_debugfs_gprwave_read,

	.open = amdgpu_debugfs_gprwave_open,

	.release = amdgpu_debugfs_gprwave_release,

	.llseek = default_llseek

};



static const struct file_operations amdgpu_debugfs_regs_fops = {

	.owner = THIS_MODULE,

	.read = amdgpu_debugfs_regs_read,
@@ -1418,6 +1582,7 @@ static const struct file_operations amdgpu_debugfs_gfxoff_residency_fops = { 
static const struct file_operations *debugfs_regs[] = {

	&amdgpu_debugfs_regs_fops,

	&amdgpu_debugfs_regs2_fops,

	&amdgpu_debugfs_gprwave_fops,

	&amdgpu_debugfs_regs_didt_fops,

	&amdgpu_debugfs_regs_pcie_fops,

	&amdgpu_debugfs_regs_smc_fops,
@@ -1434,6 +1599,7 @@ static const struct file_operations *debugfs_regs[] = { 
static const char * const debugfs_regs_names[] = {

	"amdgpu_regs",

	"amdgpu_regs2",

	"amdgpu_gprwave",

	"amdgpu_regs_didt",

	"amdgpu_regs_pcie",

	"amdgpu_regs_smc",

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+5 −5
Original line number Diff line number Diff line
@@ -247,16 +247,16 @@ struct amdgpu_gfx_funcs { 
	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);

	void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,

			     u32 sh_num, u32 instance, int xcc_id);

	void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,

	void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

			       uint32_t wave, uint32_t *dst, int *no_fields);

	void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,

	void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

				uint32_t wave, uint32_t thread, uint32_t start,

				uint32_t size, uint32_t *dst);

	void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,

	void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

				uint32_t wave, uint32_t start, uint32_t size,

				uint32_t *dst);

	void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,

				 u32 queue, u32 vmid);

				 u32 queue, u32 vmid, u32 xcc_id);

	void (*init_spm_golden)(struct amdgpu_device *adev);

	void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);

	int (*get_gfx_shadow_info)(struct amdgpu_device *adev,
@@ -405,7 +405,7 @@ struct amdgpu_gfx { 


#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))

#define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id)))

#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))

#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id)))

#define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))

#define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si)))

drivers/gpu/drm/amd/amdgpu/amdgpu_umr.h

+35 −1
Original line number Diff line number Diff line
@@ -35,17 +35,51 @@ struct amdgpu_debugfs_regs2_iocdata { 
	} srbm;

};



struct amdgpu_debugfs_regs2_iocdata_v2 {

	__u32 use_srbm, use_grbm, pg_lock;

	struct {

		__u32 se, sh, instance;

	} grbm;

	struct {

		__u32 me, pipe, queue, vmid;

	} srbm;

	u32 xcc_id;

};



struct amdgpu_debugfs_gprwave_iocdata {

	u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id;

	struct {

		u32 thread, vpgr_or_sgpr;

	} gpr;

};



/*

 * MMIO debugfs state data (per file* handle)

 */

struct amdgpu_debugfs_regs2_data {

	struct amdgpu_device *adev;

	struct mutex lock;

	struct amdgpu_debugfs_regs2_iocdata id;

	struct amdgpu_debugfs_regs2_iocdata_v2 id;

};



struct amdgpu_debugfs_gprwave_data {

	struct amdgpu_device *adev;

	struct mutex lock;

	struct amdgpu_debugfs_gprwave_iocdata id;

};



enum AMDGPU_DEBUGFS_REGS2_CMDS {

	AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE=0,

	AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE_V2,

};



enum AMDGPU_DEBUGFS_GPRWAVE_CMDS {

	AMDGPU_DEBUGFS_GPRWAVE_CMD_SET_STATE=0,

};



//reg2 interface

#define AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE _IOWR(0x20, AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE, struct amdgpu_debugfs_regs2_iocdata)

#define AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE_V2 _IOWR(0x20, AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE_V2, struct amdgpu_debugfs_regs2_iocdata_v2)



//gprwave interface

#define AMDGPU_DEBUGFS_GPRWAVE_IOC_SET_STATE _IOWR(0x20, AMDGPU_DEBUGFS_GPRWAVE_CMD_SET_STATE, struct amdgpu_debugfs_gprwave_iocdata)

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+4 −4
Original line number Diff line number Diff line
@@ -4291,7 +4291,7 @@ static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 
		*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);

}



static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)

static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)

{

	/* in gfx10 the SIMD_ID is specified as part of the INSTANCE

	 * field when performing a select_se_sh so it should be
@@ -4318,7 +4318,7 @@ static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, 
	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);

}



static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,

static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

				     uint32_t wave, uint32_t start,

				     uint32_t size, uint32_t *dst)

{
@@ -4329,7 +4329,7 @@ static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 
		dst);

}



static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,

static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

				      uint32_t wave, uint32_t thread,

				      uint32_t start, uint32_t size,

				      uint32_t *dst)
@@ -4340,7 +4340,7 @@ static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 
}



static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,

				       u32 me, u32 pipe, u32 q, u32 vm)

				       u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

{

	nv_grbm_select(adev, me, pipe, q, vm);

}

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+4 −4
Original line number Diff line number Diff line
@@ -765,7 +765,7 @@ static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 
		*(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);

}



static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)

static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)

{

	/* in gfx11 the SIMD_ID is specified as part of the INSTANCE

	 * field when performing a select_se_sh so it should be
@@ -791,7 +791,7 @@ static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, 
	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);

}



static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,

static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

				     uint32_t wave, uint32_t start,

				     uint32_t size, uint32_t *dst)

{
@@ -802,7 +802,7 @@ static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 
		dst);

}



static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,

static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

				      uint32_t wave, uint32_t thread,

				      uint32_t start, uint32_t size,

				      uint32_t *dst)
@@ -813,7 +813,7 @@ static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 
}



static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev,

									  u32 me, u32 pipe, u32 q, u32 vm)

					u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)

{

	soc21_grbm_select(adev, me, pipe, q, vm);

}