Commit 557be501 authored by Peng Fan's avatar Peng Fan Committed by Abel Vesa
Browse files

clk: imx: fracn-gppll: correct PLL initialization flow 



Per i.MX93 Reference Mannual 22.4 Initialization information
1. Program appropriate value of DIV[ODIV], DIV[RDIV] and DIV[MFI]
   as per Integer mode.
2. Wait for 5 μs.
3. Program the following field in CTRL register.
   Set CTRL[POWERUP] to 1'b1 to enable PLL block.
4. Poll PLL_STATUS[PLL_LOCK] register, and wait till PLL_STATUS[PLL_LOCK]
   is 1'b1 and pll_lock output signal is 1'b1.
5. Set CTRL[CLKMUX_EN] to 1'b1 to enable PLL output clock.

So move the CLKMUX_EN operation after PLL locked.

Fixes: 1b26cb8a ("clk: imx: support fracn gppll")
Co-developed-by: default avatarJacky Bai <ping.bai@nxp.com>
Signed-off-by: default avatarJacky Bai <ping.bai@nxp.com>
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Reviewed-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20241027-imx-clk-v1-v3-2-89152574d1d7@nxp.com


Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
parent 5ee063fa

drivers/clk/imx/clk-fracn-gppll.c

+3 −3
Original line number Diff line number Diff line
@@ -303,13 +303,13 @@ static int clk_fracn_gppll_prepare(struct clk_hw *hw) 
	val |= POWERUP_MASK;

	writel_relaxed(val, pll->base + PLL_CTRL);



	val |= CLKMUX_EN;

	writel_relaxed(val, pll->base + PLL_CTRL);



	ret = clk_fracn_gppll_wait_lock(pll);

	if (ret)

		return ret;



	val |= CLKMUX_EN;

	writel_relaxed(val, pll->base + PLL_CTRL);



	val &= ~CLKMUX_BYPASS;

	writel_relaxed(val, pll->base + PLL_CTRL);