Commit 56613001 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux 

Tariq Toukan says:

====================
mlx5-next updates 2025-07-22

The following pull-request contains common mlx5 updates

* 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux:
  net/mlx5: Expose cable_length field in PFCC register
  net/mlx5: Add IFC bits and enums for buf_ownership
  net/mlx5: Add IFC bits to support RSS for IPSec offload
====================

Link: https://patch.msgid.link/1753175048-330044-1-git-send-email-tariqt@nvidia.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 9f9a14a8 9a0048e0

drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c

+8 −5
Original line number Diff line number Diff line
@@ -727,8 +727,9 @@ hws_definer_conv_outer(struct mlx5hws_definer_conv_data *cd, 
	u32 *s_ipv6, *d_ipv6;



	if (HWS_IS_FLD_SET_SZ(match_param, outer_headers.l4_type, 0x2) ||

	    HWS_IS_FLD_SET_SZ(match_param, outer_headers.reserved_at_c2, 0xe) ||

	    HWS_IS_FLD_SET_SZ(match_param, outer_headers.reserved_at_c4, 0x4)) {

	    HWS_IS_FLD_SET_SZ(match_param, outer_headers.l4_type_ext, 0x4) ||

	    HWS_IS_FLD_SET_SZ(match_param, outer_headers.reserved_at_c6, 0xa) ||

	    HWS_IS_FLD_SET_SZ(match_param, outer_headers.reserved_at_d4, 0x4)) {

		mlx5hws_err(cd->ctx, "Unsupported outer parameters set\n");

		return -EINVAL;

	}
@@ -903,8 +904,9 @@ hws_definer_conv_inner(struct mlx5hws_definer_conv_data *cd, 
	u32 *s_ipv6, *d_ipv6;



	if (HWS_IS_FLD_SET_SZ(match_param, inner_headers.l4_type, 0x2) ||

	    HWS_IS_FLD_SET_SZ(match_param, inner_headers.reserved_at_c2, 0xe) ||

	    HWS_IS_FLD_SET_SZ(match_param, inner_headers.reserved_at_c4, 0x4)) {

	    HWS_IS_FLD_SET_SZ(match_param, inner_headers.l4_type_ext, 0x4) ||

	    HWS_IS_FLD_SET_SZ(match_param, inner_headers.reserved_at_c6, 0xa) ||

	    HWS_IS_FLD_SET_SZ(match_param, inner_headers.reserved_at_d4, 0x4)) {

		mlx5hws_err(cd->ctx, "Unsupported inner parameters set\n");

		return -EINVAL;

	}
@@ -1279,7 +1281,8 @@ hws_definer_conv_misc2(struct mlx5hws_definer_conv_data *cd, 
	struct mlx5hws_definer_fc *curr_fc;



	if (HWS_IS_FLD_SET_SZ(match_param, misc_parameters_2.reserved_at_1a0, 0x8) ||

	    HWS_IS_FLD_SET_SZ(match_param, misc_parameters_2.reserved_at_1b8, 0x8) ||

	    HWS_IS_FLD_SET_SZ(match_param,

			      misc_parameters_2.ipsec_next_header, 0x8) ||

	    HWS_IS_FLD_SET_SZ(match_param, misc_parameters_2.reserved_at_1c0, 0x40) ||

	    HWS_IS_FLD_SET(match_param, misc_parameters_2.macsec_syndrome) ||

	    HWS_IS_FLD_SET(match_param, misc_parameters_2.ipsec_syndrome)) {

include/linux/mlx5/mlx5_ifc.h

+45 −13
Original line number Diff line number Diff line
@@ -420,7 +420,8 @@ struct mlx5_ifc_flow_table_fields_supported_bits { 


/* Table 2170 - Flow Table Fields Supported 2 Format */

struct mlx5_ifc_flow_table_fields_supported_2_bits {

	u8         reserved_at_0[0x2];

	u8         inner_l4_type_ext[0x1];

	u8         outer_l4_type_ext[0x1];

	u8         inner_l4_type[0x1];

	u8         outer_l4_type[0x1];

	u8         reserved_at_4[0xa];
@@ -429,7 +430,11 @@ struct mlx5_ifc_flow_table_fields_supported_2_bits { 
	u8         tunnel_header_0_1[0x1];

	u8         reserved_at_11[0xf];



	u8         reserved_at_20[0x60];

	u8         reserved_at_20[0xf];

	u8         ipsec_next_header[0x1];

	u8         reserved_at_30[0x10];



	u8         reserved_at_40[0x40];

};



struct mlx5_ifc_flow_table_prop_layout_bits {
@@ -552,6 +557,13 @@ enum { 
	MLX5_PACKET_L4_TYPE_UDP,

};



enum {

	MLX5_PACKET_L4_TYPE_EXT_NONE,

	MLX5_PACKET_L4_TYPE_EXT_TCP,

	MLX5_PACKET_L4_TYPE_EXT_UDP,

	MLX5_PACKET_L4_TYPE_EXT_ICMP,

};



struct mlx5_ifc_fte_match_set_lyr_2_4_bits {

	u8         smac_47_16[0x20];
@@ -578,10 +590,10 @@ struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 
	u8         tcp_dport[0x10];



	u8         l4_type[0x2];

	u8         reserved_at_c2[0xe];

	u8         l4_type_ext[0x4];

	u8         reserved_at_c6[0xa];

	u8         ipv4_ihl[0x4];

	u8         reserved_at_c4[0x4];



	u8         reserved_at_d4[0x4];

	u8         ttl_hoplimit[0x8];



	u8         udp_sport[0x10];
@@ -689,10 +701,9 @@ struct mlx5_ifc_fte_match_set_misc2_bits { 
	u8         metadata_reg_a[0x20];



	u8         reserved_at_1a0[0x8];



	u8         macsec_syndrome[0x8];

	u8         ipsec_syndrome[0x8];

	u8         reserved_at_1b8[0x8];

	u8         ipsec_next_header[0x8];



	u8         reserved_at_1c0[0x40];

};
@@ -9983,6 +9994,10 @@ struct mlx5_ifc_pude_reg_bits { 
	u8         reserved_at_20[0x60];

};



enum {

	MLX5_PTYS_CONNECTOR_TYPE_PORT_DA = 0x7,

};



struct mlx5_ifc_ptys_reg_bits {

	u8         reserved_at_0[0x1];

	u8         an_disable_admin[0x1];
@@ -10019,7 +10034,8 @@ struct mlx5_ifc_ptys_reg_bits { 
	u8         ib_link_width_oper[0x10];

	u8         ib_proto_oper[0x10];



	u8         reserved_at_160[0x1c];

	u8         reserved_at_160[0x8];

	u8         lane_rate_oper[0x14];

	u8         connector_type[0x4];



	u8         eth_proto_lp_advertise[0x20];
@@ -10463,10 +10479,19 @@ struct mlx5_ifc_pifr_reg_bits { 
	u8         port_filter_update_en[8][0x20];

};



enum {

	MLX5_BUF_OWNERSHIP_UNKNOWN	= 0x0,

	MLX5_BUF_OWNERSHIP_FW_OWNED	= 0x1,

	MLX5_BUF_OWNERSHIP_SW_OWNED	= 0x2,

};



struct mlx5_ifc_pfcc_reg_bits {

	u8         reserved_at_0[0x8];

	u8         reserved_at_0[0x4];

	u8	   buf_ownership[0x2];

	u8	   reserved_at_6[0x2];

	u8         local_port[0x8];

	u8         reserved_at_10[0xb];

	u8         reserved_at_10[0xa];

	u8	   cable_length_mask[0x1];

	u8         ppan_mask_n[0x1];

	u8         minor_stall_mask[0x1];

	u8         critical_stall_mask[0x1];
@@ -10495,7 +10520,10 @@ struct mlx5_ifc_pfcc_reg_bits { 
	u8         device_stall_minor_watermark[0x10];

	u8         device_stall_critical_watermark[0x10];



	u8         reserved_at_a0[0x60];

	u8	   reserved_at_a0[0x18];

	u8	   cable_length[0x8];



	u8         reserved_at_c0[0x40];

};



struct mlx5_ifc_pelc_reg_bits {
@@ -10596,11 +10624,15 @@ struct mlx5_ifc_mtutc_reg_bits { 
struct mlx5_ifc_pcam_enhanced_features_bits {

	u8         reserved_at_0[0x10];

	u8         ppcnt_recovery_counters[0x1];

	u8         reserved_at_11[0xc];

	u8         reserved_at_11[0x7];

	u8	   cable_length[0x1];

	u8	   reserved_at_19[0x4];

	u8         fec_200G_per_lane_in_pplm[0x1];

	u8         reserved_at_1e[0x2a];

	u8         fec_100G_per_lane_in_pplm[0x1];

	u8         reserved_at_49[0x1f];

	u8         reserved_at_49[0xa];

	u8	   buffer_ownership[0x1];

	u8	   resereved_at_54[0x14];

	u8         fec_50G_per_lane_in_pplm[0x1];

	u8         reserved_at_69[0x4];

	u8         rx_icrc_encapsulated_counter[0x1];