Commit 5679dd24 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2023-10-26' of... 

Merge tag 'drm-intel-fixes-2023-10-26' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

- Determine context valid in OA reports (Umesh)
- Hold GT forcewake during steering operations (Matt Roper)
- Check if PMU is closed before stopping event (Umesh)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZTp8IQ0wxzxVjN7J@intel.com
parents 6366ffa6 4cbed770

drivers/gpu/drm/i915/gt/intel_gt_mcr.c

+22 −2
Original line number Diff line number Diff line
@@ -376,9 +376,26 @@ void intel_gt_mcr_lock(struct intel_gt *gt, unsigned long *flags) 
	 * driver threads, but also with hardware/firmware agents.  A dedicated

	 * locking register is used.

	 */

	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))

	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) {

		/*

		 * The steering control and semaphore registers are inside an

		 * "always on" power domain with respect to RC6.  However there

		 * are some issues if higher-level platform sleep states are

		 * entering/exiting at the same time these registers are

		 * accessed.  Grabbing GT forcewake and holding it over the

		 * entire lock/steer/unlock cycle ensures that those sleep

		 * states have been fully exited before we access these

		 * registers.  This wakeref will be released in the unlock

		 * routine.

		 *

		 * This is expected to become a formally documented/numbered

		 * workaround soon.

		 */

		intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_GT);



		err = wait_for(intel_uncore_read_fw(gt->uncore,

						    MTL_STEER_SEMAPHORE) == 0x1, 100);

	}



	/*

	 * Even on platforms with a hardware lock, we'll continue to grab
@@ -415,8 +432,11 @@ void intel_gt_mcr_unlock(struct intel_gt *gt, unsigned long flags) 
{

	spin_unlock_irqrestore(&gt->mcr_lock, flags);



	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))

	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) {

		intel_uncore_write_fw(gt->uncore, MTL_STEER_SEMAPHORE, 0x1);



		intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_GT);

	}

}



/**

drivers/gpu/drm/i915/i915_perf.c

+2 −2
Original line number Diff line number Diff line
@@ -482,8 +482,7 @@ static void oa_report_id_clear(struct i915_perf_stream *stream, u32 *report) 
static bool oa_report_ctx_invalid(struct i915_perf_stream *stream, void *report)

{

	return !(oa_report_id(stream, report) &

	       stream->perf->gen8_valid_ctx_bit) &&

	       GRAPHICS_VER(stream->perf->i915) <= 11;

	       stream->perf->gen8_valid_ctx_bit);

}



static u64 oa_timestamp(struct i915_perf_stream *stream, void *report)
@@ -5106,6 +5105,7 @@ static void i915_perf_init_info(struct drm_i915_private *i915) 
		perf->gen8_valid_ctx_bit = BIT(16);

		break;

	case 12:

		perf->gen8_valid_ctx_bit = BIT(16);

		/*

		 * Calculate offset at runtime in oa_pin_context for gen12 and

		 * cache the value in perf->ctx_oactxctrl_offset.

drivers/gpu/drm/i915/i915_pmu.c

+9 −0
Original line number Diff line number Diff line
@@ -832,9 +832,18 @@ static void i915_pmu_event_start(struct perf_event *event, int flags) 


static void i915_pmu_event_stop(struct perf_event *event, int flags)

{

	struct drm_i915_private *i915 =

		container_of(event->pmu, typeof(*i915), pmu.base);

	struct i915_pmu *pmu = &i915->pmu;



	if (pmu->closed)

		goto out;



	if (flags & PERF_EF_UPDATE)

		i915_pmu_event_read(event);

	i915_pmu_disable(event);



out:

	event->hw.state = PERF_HES_STOPPED;

}