Merge tag 'drm-next-2021-11-03' of git://anongit.freedesktop.org/drm/drm

  compatible:

    enum:

      - qcom,sc7180-dp

      - qcom,sc8180x-dp

      - qcom,sc8180x-edp

  reg:

    maxItems: 1

    items:

      - description: ahb register block

      - description: aux register block

      - description: link register block

      - description: p0 register block

      - description: p1 register block

  interrupts:

    maxItems: 1

    displayport-controller@ae90000 {

        compatible = "qcom,sc7180-dp";

        reg = <0xae90000 0x1400>;

        reg = <0xae90000 0x200>,

              <0xae90200 0x200>,

              <0xae90400 0xc00>,

              <0xae91000 0x400>,

              <0xae91400 0x400>;

        interrupt-parent = <&mdss>;

        interrupts = <12>;

        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DPU dt properties for SC7280

maintainers:

  - Krishna Manikandan <mkrishn@codeaurora.org>

description: |

  Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates

  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree

  bindings of MDSS and DPU are mentioned for SC7280.

properties:

  compatible:

    const: qcom,sc7280-mdss

  reg:

    maxItems: 1

  reg-names:

    const: mdss

  power-domains:

    maxItems: 1

  clocks:

    items:

      - description: Display AHB clock from gcc

      - description: Display AHB clock from dispcc

      - description: Display core clock

  clock-names:

    items:

      - const: iface

      - const: ahb

      - const: core

  interrupts:

    maxItems: 1

  interrupt-controller: true

  "#address-cells": true

  "#size-cells": true

  "#interrupt-cells":

    const: 1

  iommus:

    items:

      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0

  ranges: true

  interconnects:

    items:

      - description: Interconnect path specifying the port ids for data bus

  interconnect-names:

    const: mdp0-mem

patternProperties:

  "^display-controller@[0-9a-f]+$":

    type: object

    description: Node containing the properties of DPU.

    properties:

      compatible:

        const: qcom,sc7280-dpu

      reg:

        items:

          - description: Address offset and size for mdp register set

          - description: Address offset and size for vbif register set

      reg-names:

        items:

          - const: mdp

          - const: vbif

      clocks:

        items:

          - description: Display hf axi clock

          - description: Display sf axi clock

          - description: Display ahb clock

          - description: Display lut clock

          - description: Display core clock

          - description: Display vsync clock

      clock-names:

        items:

          - const: bus

          - const: nrt_bus

          - const: iface

          - const: lut

          - const: core

          - const: vsync

      interrupts:

        maxItems: 1

      power-domains:

        maxItems: 1

      operating-points-v2: true

      ports:

        $ref: /schemas/graph.yaml#/properties/ports

        description: |

          Contains the list of output ports from DPU device. These ports

          connect to interfaces that are external to the DPU hardware,

          such as DSI, DP etc. Each output port contains an endpoint that

          describes how it is connected to an external interface.

        properties:

          port@0:

            $ref: /schemas/graph.yaml#/properties/port

            description: DPU_INTF1 (DSI)

          port@1:

            $ref: /schemas/graph.yaml#/properties/port

            description: DPU_INTF5 (EDP)

        required:

          - port@0

    required:

      - compatible

      - reg

      - reg-names

      - clocks

      - interrupts

      - power-domains

      - operating-points-v2

      - ports

required:

  - compatible

  - reg

  - reg-names

  - power-domains

  - clocks

  - interrupts

  - interrupt-controller

  - iommus

  - ranges

additionalProperties: false

examples:

  - |

    #include <dt-bindings/clock/qcom,dispcc-sc7280.h>

    #include <dt-bindings/clock/qcom,gcc-sc7280.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interconnect/qcom,sc7280.h>

    #include <dt-bindings/power/qcom-rpmpd.h>

    display-subsystem@ae00000 {

         #address-cells = <1>;

         #size-cells = <1>;

         compatible = "qcom,sc7280-mdss";

         reg = <0xae00000 0x1000>;

         reg-names = "mdss";

         power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;

         clocks = <&gcc GCC_DISP_AHB_CLK>,

                  <&dispcc DISP_CC_MDSS_AHB_CLK>,

                  <&dispcc DISP_CC_MDSS_MDP_CLK>;

         clock-names = "iface",

                       "ahb",

                       "core";

         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

         interrupt-controller;

         #interrupt-cells = <1>;

         interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;

         interconnect-names = "mdp0-mem";

         iommus = <&apps_smmu 0x900 0x402>;

         ranges;

         display-controller@ae01000 {

                   compatible = "qcom,sc7280-dpu";

                   reg = <0x0ae01000 0x8f000>,

                         <0x0aeb0000 0x2008>;

                   reg-names = "mdp", "vbif";

                   clocks = <&gcc GCC_DISP_HF_AXI_CLK>,

                            <&gcc GCC_DISP_SF_AXI_CLK>,

                            <&dispcc DISP_CC_MDSS_AHB_CLK>,

                            <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,

                            <&dispcc DISP_CC_MDSS_MDP_CLK>,

                            <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

                   clock-names = "bus",

                                 "nrt_bus",

                                 "iface",

                                 "lut",

                                 "core",

                                 "vsync";

                   interrupt-parent = <&mdss>;

                   interrupts = <0>;

                   power-domains = <&rpmhpd SC7280_CX>;

                   operating-points-v2 = <&mdp_opp_table>;

                   ports {

                           #address-cells = <1>;

                           #size-cells = <0>;

                           port@0 {

                                   reg = <0>;

                                   dpu_intf1_out: endpoint {

                                           remote-endpoint = <&dsi0_in>;

                                   };

                           };

                           port@1 {

                                   reg = <1>;

                                   dpu_intf5_out: endpoint {

                                           remote-endpoint = <&edp_in>;

                                   };

                           };

                   };

         };

    };

...

    enum:

      - qcom,dsi-phy-14nm

      - qcom,dsi-phy-14nm-660

      - qcom,dsi-phy-14nm-8953

  reg:

    items:

Qualcomm adreno/snapdragon GPU

Required properties:

- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or

	      "amd,imageon-XYZ.W", "amd,imageon"

    for example: "qcom,adreno-306.0", "qcom,adreno"

  Note that you need to list the less specific "qcom,adreno" (since this

  is what the device is matched on), in addition to the more specific

  with the chip-id.

  If "amd,imageon" is used, there should be no top level msm device.

- reg: Physical base address and length of the controller's registers.

- interrupts: The interrupt signal from the gpu.

- clocks: device clocks (if applicable)

  See ../clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required by a3xx, a4xx and a5xx

  cores:

  * "core"

  * "iface"

  * "mem_iface"

  For GMU attached devices the GPU clocks are not used and are not required. The

  following devices should not list clocks:

   - qcom,adreno-630.2

- iommus: optional phandle to an adreno iommu instance

- operating-points-v2: optional phandle to the OPP operating points

- interconnects: optional phandle to an interconnect provider.  See

  ../interconnect/interconnect.txt for details. Some A3xx and all A4xx platforms

  will have two paths; all others will have one path.

- interconnect-names: The names of the interconnect paths that correspond to the

  interconnects property. Values must be gfx-mem and ocmem.

- qcom,gmu: For GMU attached devices a phandle to the GMU device that will

  control the power for the GPU. Applicable targets:

    - qcom,adreno-630.2

- zap-shader: For a5xx and a6xx devices this node contains a memory-region that

  points to reserved memory to store the zap shader that can be used to help

  bring the GPU out of secure mode.

- firmware-name: optional property of the 'zap-shader' node, listing the

  relative path of the device specific zap firmware.

- sram: phandle to the On Chip Memory (OCMEM) that's present on some a3xx and

        a4xx Snapdragon SoCs. See

        Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.

Optional properties:

- #cooling-cells: The value must be 2. For details, please refer

	Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml.

Example 3xx/4xx:

/ {

	...

	gpu: adreno@fdb00000 {

		compatible = "qcom,adreno-330.2",

		             "qcom,adreno";

		reg = <0xfdb00000 0x10000>;

		reg-names = "kgsl_3d0_reg_memory";

		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "kgsl_3d0_irq";

		clock-names = "core",

		              "iface",

		              "mem_iface";

		clocks = <&mmcc OXILI_GFX3D_CLK>,

		         <&mmcc OXILICX_AHB_CLK>,

		         <&mmcc OXILICX_AXI_CLK>;

		sram = <&gpu_sram>;

		power-domains = <&mmcc OXILICX_GDSC>;

		operating-points-v2 = <&gpu_opp_table>;

		iommus = <&gpu_iommu 0>;

		#cooling-cells = <2>;

	};

	gpu_sram: ocmem@fdd00000 {

		compatible = "qcom,msm8974-ocmem";

		reg = <0xfdd00000 0x2000>,

		      <0xfec00000 0x180000>;

		reg-names = "ctrl",

		            "mem";

		clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,

		         <&mmcc OCMEMCX_OCMEMNOC_CLK>;

		clock-names = "core",

		              "iface";

		#address-cells = <1>;

		#size-cells = <1>;

		gpu_sram: gpu-sram@0 {

			reg = <0x0 0x100000>;

			ranges = <0 0 0xfec00000 0x100000>;

		};

	};

};

Example a6xx (with GMU):

/ {

	...

	gpu@5000000 {

		compatible = "qcom,adreno-630.2", "qcom,adreno";

		#stream-id-cells = <16>;

		reg = <0x5000000 0x40000>, <0x509e000 0x10>;

		reg-names = "kgsl_3d0_reg_memory", "cx_mem";

		#cooling-cells = <2>;

		/*

		 * Look ma, no clocks! The GPU clocks and power are

		 * controlled entirely by the GMU

		 */

		interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

		iommus = <&adreno_smmu 0>;

		operating-points-v2 = <&gpu_opp_table>;

		interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;

		interconnect-names = "gfx-mem";

		gpu_opp_table: opp-table {

			compatible = "operating-points-v2";

			opp-430000000 {

				opp-hz = /bits/ 64 <430000000>;

				opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

				opp-peak-kBps = <5412000>;

			};

			opp-355000000 {

				opp-hz = /bits/ 64 <355000000>;

				opp-level = <RPMH_REGULATOR_LEVEL_SVS>;

				opp-peak-kBps = <3072000>;

			};

			opp-267000000 {

				opp-hz = /bits/ 64 <267000000>;

				opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

				opp-peak-kBps = <3072000>;

			};

			opp-180000000 {

				opp-hz = /bits/ 64 <180000000>;

				opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;

				opp-peak-kBps = <1804000>;

			};

		};

		qcom,gmu = <&gmu>;

		zap-shader {

			memory-region = <&zap_shader_region>;

			firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"

		};

	};

};

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/display/msm/gpu.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Devicetree bindings for the Adreno or Snapdragon GPUs

maintainers:

  - Rob Clark <robdclark@gmail.com>

properties:

  compatible:

    oneOf:

      - description: |

          The driver is parsing the compat string for Adreno to

          figure out the gpu-id and patch level.

        items:

          - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'

          - const: qcom,adreno

      - description: |

          The driver is parsing the compat string for Imageon to

          figure out the gpu-id and patch level.

        items:

          - pattern: '^amd,imageon-200\.[0-1]$'

          - const: amd,imageon

  clocks: true

  clock-names: true

  reg:

    minItems: 1

    maxItems: 3

  reg-names:

    minItems: 1

    items:

      - const: kgsl_3d0_reg_memory

      - const: cx_mem

      - const: cx_dbgc

  interrupts:

    maxItems: 1

  interrupt-names:

    maxItems: 1

  interconnects:

    minItems: 1

    maxItems: 2

  interconnect-names:

    minItems: 1

    items:

      - const: gfx-mem

      - const: ocmem

  iommus:

    maxItems: 1

  sram:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    minItems: 1

    maxItems: 4

    description: |

      phandles to one or more reserved on-chip SRAM regions.

      phandle to the On Chip Memory (OCMEM) that's present on some a3xx and

      a4xx Snapdragon SoCs. See

      Documentation/devicetree/bindings/sram/qcom,ocmem.yaml

  operating-points-v2: true

  opp-table:

    type: object

  power-domains:

    maxItems: 1

  zap-shader:

    type: object

    description: |

      For a5xx and a6xx devices this node contains a memory-region that

      points to reserved memory to store the zap shader that can be used to

      help bring the GPU out of secure mode.

    properties:

      memory-region:

        $ref: /schemas/types.yaml#/definitions/phandle

      firmware-name:

        description: |

          Default name of the firmware to load to the remote processor.

  "#cooling-cells":

    const: 2

  nvmem-cell-names:

    maxItems: 1

  nvmem-cells:

    description: efuse registers

    maxItems: 1

  qcom,gmu:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: |

      For GMU attached devices a phandle to the GMU device that will

      control the power for the GPU.

required:

  - compatible

  - reg

  - interrupts

additionalProperties: false

allOf:

  - if:

      properties:

        compatible:

          contains:

            pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'

    then:

      properties:

        clocks:

          minItems: 2

          maxItems: 7

        clock-names:

          items:

            anyOf:

              - const: core

                description: GPU Core clock

              - const: iface

                description: GPU Interface clock

              - const: mem

                description: GPU Memory clock

              - const: mem_iface

                description: GPU Memory Interface clock

              - const: alt_mem_iface

                description: GPU Alternative Memory Interface clock

              - const: gfx3d

                description: GPU 3D engine clock

              - const: rbbmtimer

                description: GPU RBBM Timer for Adreno 5xx series

          minItems: 2

          maxItems: 7

      required:

        - clocks

        - clock-names

  - if:

      properties:

        compatible:

          contains:

            pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'

    then: # Since Adreno 6xx series clocks should be defined in GMU

      properties:

        clocks: false

        clock-names: false

examples:

  - |

    // Example a3xx/4xx:

    #include <dt-bindings/clock/qcom,mmcc-msm8974.h>

    #include <dt-bindings/clock/qcom,rpmcc.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    gpu: gpu@fdb00000 {

        compatible = "qcom,adreno-330.2", "qcom,adreno";

        reg = <0xfdb00000 0x10000>;

        reg-names = "kgsl_3d0_reg_memory";

        clock-names = "core", "iface", "mem_iface";

        clocks = <&mmcc OXILI_GFX3D_CLK>,

                 <&mmcc OXILICX_AHB_CLK>,

                 <&mmcc OXILICX_AXI_CLK>;

        interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-names = "kgsl_3d0_irq";

        sram = <&gpu_sram>;

        power-domains = <&mmcc OXILICX_GDSC>;

        operating-points-v2 = <&gpu_opp_table>;

        iommus = <&gpu_iommu 0>;

        #cooling-cells = <2>;

    };

    ocmem@fdd00000 {

        compatible = "qcom,msm8974-ocmem";

        reg = <0xfdd00000 0x2000>,

              <0xfec00000 0x180000>;

        reg-names = "ctrl", "mem";

        clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,

                 <&mmcc OCMEMCX_OCMEMNOC_CLK>;

        clock-names = "core", "iface";

        #address-cells = <1>;

        #size-cells = <1>;

        ranges = <0 0xfec00000 0x100000>;

        gpu_sram: gpu-sram@0 {

            reg = <0x0 0x100000>;

        };

    };

  - |

    // Example a6xx (with GMU):

    #include <dt-bindings/clock/qcom,gpucc-sdm845.h>

    #include <dt-bindings/clock/qcom,gcc-sdm845.h>

    #include <dt-bindings/power/qcom-rpmpd.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interconnect/qcom,sdm845.h>

    reserved-memory {

        #address-cells = <2>;

        #size-cells = <2>;

        zap_shader_region: gpu@8f200000 {

            compatible = "shared-dma-pool";

            reg = <0x0 0x90b00000 0x0 0xa00000>;

            no-map;

        };

    };

    gpu@5000000 {

        compatible = "qcom,adreno-630.2", "qcom,adreno";

        reg = <0x5000000 0x40000>, <0x509e000 0x10>;

        reg-names = "kgsl_3d0_reg_memory", "cx_mem";

        #cooling-cells = <2>;

        interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

        iommus = <&adreno_smmu 0>;

        operating-points-v2 = <&gpu_opp_table>;

        interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;

        interconnect-names = "gfx-mem";

        qcom,gmu = <&gmu>;

        gpu_opp_table: opp-table {

            compatible = "operating-points-v2";

            opp-430000000 {

                opp-hz = /bits/ 64 <430000000>;

                opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

                opp-peak-kBps = <5412000>;

            };

            opp-355000000 {

                opp-hz = /bits/ 64 <355000000>;

                opp-level = <RPMH_REGULATOR_LEVEL_SVS>;

                opp-peak-kBps = <3072000>;

            };

            opp-267000000 {

                opp-hz = /bits/ 64 <267000000>;

                opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

                opp-peak-kBps = <3072000>;

            };

            opp-180000000 {

                opp-hz = /bits/ 64 <180000000>;

                opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;

                opp-peak-kBps = <1804000>;

            };

        };

        zap-shader {

            memory-region = <&zap_shader_region>;

            firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn";

        };

    };