Commit 570a8fc2 authored by Lucas De Marchi's avatar Lucas De Marchi
Browse files

drm/xe/xe2: Add workaround 16020183090 



Graphics version 20.04, used in Lunar Lake, needs WA 16020183090 for
steppings A*. Set ENABLE_SEMAPHORE_POLL_BIT in INSTPM(RENDER_RING_BASE)
and whitelist CSBE_DEBUG_STATUS for userspace to be able to use it
and complement the workaround.

Cc: Haridhar Kalvala <haridhar.kalvala@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231207175117.2334022-1-lucas.demarchi@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent f031c3a7

drivers/gpu/drm/xe/regs/xe_engine_regs.h

+4 −0
Original line number Diff line number Diff line
@@ -83,6 +83,9 @@ 
#define RING_EMR(base)				XE_REG((base) + 0xb4)

#define RING_ESR(base)				XE_REG((base) + 0xb8)



#define INSTPM(base)				XE_REG((base) + 0xc0, XE_REG_OPTION_MASKED)

#define   ENABLE_SEMAPHORE_POLL_BIT		REG_BIT(13)



#define RING_CMD_CCTL(base)			XE_REG((base) + 0xc4, XE_REG_OPTION_MASKED)

/*

 * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
@@ -138,6 +141,7 @@ 
#define   TAIL_ADDR				0x001FFFF8



#define RING_CTX_TIMESTAMP(base)		XE_REG((base) + 0x3a8)

#define CSBE_DEBUG_STATUS(base)			XE_REG((base) + 0x3fc)



#define RING_FORCE_TO_NONPRIV(base, i)		XE_REG(((base) + 0x4d0) + (i) * 4)

#define   RING_FORCE_TO_NONPRIV_DENY		REG_BIT(30)

drivers/gpu/drm/xe/xe_reg_whitelist.c

+8 −0
Original line number Diff line number Diff line
@@ -7,9 +7,11 @@ 


#include "regs/xe_engine_regs.h"

#include "regs/xe_gt_regs.h"

#include "regs/xe_regs.h"

#include "xe_gt_types.h"

#include "xe_platform_types.h"

#include "xe_rtp.h"

#include "xe_step.h"



#undef XE_REG_MCR

#define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
@@ -56,6 +58,12 @@ static const struct xe_rtp_entry_sr register_whitelist[] = { 
				   RING_FORCE_TO_NONPRIV_DENY,

				   XE_RTP_ACTION_FLAG(ENGINE_BASE)))

	},

	{ XE_RTP_NAME("16020183090"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),

		       ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0))

	},



	{}

};

drivers/gpu/drm/xe/xe_wa.c

+5 −0
Original line number Diff line number Diff line
@@ -571,6 +571,11 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))

	},

	{ XE_RTP_NAME("16020183090"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),

		       ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))

	},



	{}

};