Commit 579483ec authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Vinod Koul
Browse files

phy: qcom-qmp-combo: fix the prefix for the PCS_USB v6 registers 



For all other generations, we have been using just the QPHY prefix for
the PCS registers. Remove the _USB part of the QPHY_USB prefix.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230928105445.1210861-2-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 9e34abc7

drivers/phy/qualcomm/phy-qcom-qmp-combo.c

+19 −19
Original line number Diff line number Diff line
@@ -845,28 +845,28 @@ static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = { 
};



static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RX_SIGDET_LVL, 0x99),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_CDR_RESET_TIME, 0x0a),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG1, 0x4b),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG5, 0x10),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x99),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),

};



static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),

	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68),

};



static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {

drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h

+20 −20
Original line number Diff line number Diff line
@@ -7,26 +7,26 @@ 
#define QCOM_PHY_QMP_PCS_USB_V6_H_



/* Only for QMP V6 PHY - USB3 have different offsets than V5 */

#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1		0xc4

#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2		0xc8

#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3		0xcc

#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6		0xd8

#define QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1		0xdc

#define QPHY_USB_V6_PCS_POWER_STATE_CONFIG1		0x90

#define QPHY_USB_V6_PCS_RX_SIGDET_LVL			0x188

#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L		0x190

#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H		0x194

#define QPHY_USB_V6_PCS_CDR_RESET_TIME			0x1b0

#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1		0x1c0

#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2		0x1c4

#define QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG		0x1d0

#define QPHY_USB_V6_PCS_EQ_CONFIG1			0x1dc

#define QPHY_USB_V6_PCS_EQ_CONFIG5			0x1ec

#define QPHY_V6_PCS_LOCK_DETECT_CONFIG1		0xc4

#define QPHY_V6_PCS_LOCK_DETECT_CONFIG2		0xc8

#define QPHY_V6_PCS_LOCK_DETECT_CONFIG3		0xcc

#define QPHY_V6_PCS_LOCK_DETECT_CONFIG6		0xd8

#define QPHY_V6_PCS_REFGEN_REQ_CONFIG1		0xdc

#define QPHY_V6_PCS_POWER_STATE_CONFIG1		0x90

#define QPHY_V6_PCS_RX_SIGDET_LVL			0x188

#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L		0x190

#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H		0x194

#define QPHY_V6_PCS_CDR_RESET_TIME			0x1b0

#define QPHY_V6_PCS_ALIGN_DETECT_CONFIG1		0x1c0

#define QPHY_V6_PCS_ALIGN_DETECT_CONFIG2		0x1c4

#define QPHY_V6_PCS_PCS_TX_RX_CONFIG		0x1d0

#define QPHY_V6_PCS_EQ_CONFIG1			0x1dc

#define QPHY_V6_PCS_EQ_CONFIG5			0x1ec



#define QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1	0x00

#define QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0x18

#define QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x3c

#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L		0x40

#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H		0x44

#define QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1		0x00

#define QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0x18

#define QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x3c

#define QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L		0x40

#define QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H		0x44



#endif