Documentation: admin-guide: Add riscv sysctl_perf_user_access

The default value is 8.

perf_user_access (arm64 only)

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perf_user_access (arm64 and riscv only)

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Controls user space access for reading perf event counters.

Controls user space access for reading perf event counters. When set to 1,

user space can read performance monitor counter registers directly.

arm64

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The default value is 0 (access disabled).

When set to 1, user space can read performance monitor counter registers

directly.

See Documentation/arch/arm64/perf.rst for more information.

riscv

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When set to 0, user space access is disabled.

The default value is 1, user space can read performance monitor counter

registers through perf, any direct access without perf intervention will trigger

an illegal instruction.

When set to 2, which enables legacy mode (user space has direct access to cycle

and insret CSRs only). Note that this legacy value is deprecated and will be

removed once all user space applications are fixed.

Note that the time CSR is always directly accessible to all modes.

pid_max

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