Commit 579951da authored by Junhui Liu's avatar Junhui Liu Committed by Thomas Gleixner
Browse files

dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI 



Add MSWI support for Anlogic DR1V90 SoC, which uses Nuclei UX900 with a
TIMER unit compliant with the ACLINT specification.

Signed-off-by: default avatarJunhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Acked-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251021-dr1v90-basic-dt-v3-5-5478db4f664a@pigmoral.tech
parent b90ac5fe

Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml

+11 −6
Original line number Diff line number Diff line
@@ -4,18 +4,23 @@ 
$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device

title: ACLINT Machine-level Software Interrupt Device



maintainers:

  - Inochi Amaoto <inochiama@outlook.com>



properties:

  compatible:

    items:

    oneOf:

      - items:

          - enum:

              - sophgo,sg2042-aclint-mswi

              - sophgo,sg2044-aclint-mswi

          - const: thead,c900-aclint-mswi

      - items:

          - enum:

              - anlogic,dr1v90-aclint-mswi

          - const: nuclei,ux900-aclint-mswi



  reg:

    maxItems: 1