Commit 57d298bd authored by Mikko Perttunen's avatar Mikko Perttunen Committed by Thierry Reding
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gpu: host1x: Add MLOCK recovery for rest of engines



Add class IDs / MLOCKs for MLOCK recovery for rest of engines
present on Tegra234.

Signed-off-by: default avatarMikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240425050238.2943404-4-cyndis@kapsi.fi
parent 4e90b03a
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+12 −0
Original line number Diff line number Diff line
@@ -254,12 +254,24 @@ static void timeout_release_mlock(struct host1x_cdma *cdma)
	u32 offset;

	switch (ch->client->class) {
	case HOST1X_CLASS_NVJPG1:
		offset = HOST1X_COMMON_NVJPG1_MLOCK;
		break;
	case HOST1X_CLASS_NVENC:
		offset = HOST1X_COMMON_NVENC_MLOCK;
		break;
	case HOST1X_CLASS_VIC:
		offset = HOST1X_COMMON_VIC_MLOCK;
		break;
	case HOST1X_CLASS_NVJPG:
		offset = HOST1X_COMMON_NVJPG_MLOCK;
		break;
	case HOST1X_CLASS_NVDEC:
		offset = HOST1X_COMMON_NVDEC_MLOCK;
		break;
	case HOST1X_CLASS_OFA:
		offset = HOST1X_COMMON_OFA_MLOCK;
		break;
	default:
		WARN(1, "%s was not updated for class %u", __func__, ch->client->class);
		return;
+5 −0
Original line number Diff line number Diff line
@@ -14,12 +14,17 @@

enum host1x_class {
	HOST1X_CLASS_HOST1X = 0x1,
	HOST1X_CLASS_NVJPG1 = 0x7,
	HOST1X_CLASS_NVENC = 0x21,
	HOST1X_CLASS_NVENC1 = 0x22,
	HOST1X_CLASS_GR2D = 0x51,
	HOST1X_CLASS_GR2D_SB = 0x52,
	HOST1X_CLASS_VIC = 0x5D,
	HOST1X_CLASS_GR3D = 0x60,
	HOST1X_CLASS_NVJPG = 0xC0,
	HOST1X_CLASS_NVDEC = 0xF0,
	HOST1X_CLASS_NVDEC1 = 0xF5,
	HOST1X_CLASS_OFA = 0xF8,
};

struct host1x;