Commit 58052eb7 authored by Lucas De Marchi's avatar Lucas De Marchi Committed by Rodrigo Vivi
Browse files

drm/xe: Fix MTL+ stolen memory mapping 



Based on commit 8d8d062b ("drm/i915/mtl: Fix MTL stolen memory GGTT
mapping"). For stolen on MTL and beyond, the address in the PTE is the
offset from DSM base. While at it, update the comments explaining each
part of the calculation.

Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230726160708.3967790-9-lucas.demarchi@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent b23ebae7

drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c

+13 −2
Original line number Diff line number Diff line
@@ -94,11 +94,22 @@ static u32 detect_bar2_integrated(struct xe_device *xe, struct xe_ttm_stolen_mgr 


	ggc = xe_mmio_read32(xe_root_mmio_gt(xe), GGC);



	/* check GGMS, should be fixed 0x3 (8MB) */

	/*

	 * Check GGMS: it should be fixed 0x3 (8MB), which corresponds to the

	 * GTT size

	 */

	if (drm_WARN_ON(&xe->drm, (ggc & GGMS_MASK) != GGMS_MASK))

		return 0;



	mgr->stolen_base = mgr->io_base = pci_resource_start(pdev, 2) + SZ_8M;

	/*

	 * Graphics >= 1270 uses the offset to the GSMBASE as address in the

	 * PTEs, together with the DM flag being set. Previously there was no

	 * such flag so the address was the io_base.

	 *

	 * DSMBASE = GSMBASE + 8MB

	 */

	mgr->stolen_base = SZ_8M;

	mgr->io_base = pci_resource_start(pdev, 2) + mgr->stolen_base;



	/* return valid GMS value, -EIO if invalid */

	gms = REG_FIELD_GET(GMS_MASK, ggc);