Commit 580e3137 authored by Tom Rix's avatar Tom Rix Committed by Moritz Fischer
Browse files

fpga: fix spelling mistakes 



Run the fpga subsystem through aspell.

Signed-off-by: default avatarTom Rix <trix@redhat.com>
Reviewed-by: default avatarFernando Pacheco <fpacheco@redhat.com>
Signed-off-by: default avatarMoritz Fischer <mdf@kernel.org>
parent 758f7467

Documentation/fpga/dfl.rst

+2 −2
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ Authors: 
- Xu Yilun <yilun.xu@intel.com>



The Device Feature List (DFL) FPGA framework (and drivers according to

this framework) hides the very details of low layer hardwares and provides

this framework) hides the very details of low layer hardware and provides

unified interfaces to userspace. Applications could use these interfaces to

configure, enumerate, open and access FPGA accelerators on platforms which

implement the DFL in the device memory. Besides this, the DFL framework
@@ -205,7 +205,7 @@ given Device Feature Lists and create platform devices for feature devices 
also abstracts operations for the private features and exposes common ops to

feature device drivers.



The FPGA DFL Device could be different hardwares, e.g. PCIe device, platform

The FPGA DFL Device could be different hardware, e.g. PCIe device, platform

device and etc. Its driver module is always loaded first once the device is

created by the system. This driver plays an infrastructural role in the

driver architecture. It locates the DFLs in the device memory, handles them

drivers/fpga/dfl-fme-pr.c

+1 −1
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@@ -148,7 +148,7 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg) 


	/*

	 * it allows userspace to reset the PR region's logic by disabling and

	 * reenabling the bridge to clear things out between accleration runs.

	 * reenabling the bridge to clear things out between acceleration runs.

	 * so no need to hold the bridges after partial reconfiguration.

	 */

	if (region->get_bridges)

drivers/fpga/dfl-n3000-nios.c

+1 −1
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@@ -461,7 +461,7 @@ static int n3000_nios_poll_stat_timeout(void __iomem *base, u64 *v) 
	 * We don't use the time based timeout here for performance.

	 *

	 * The regbus read/write is on the critical path of Intel PAC N3000

	 * image programing. The time based timeout checking will add too much

	 * image programming. The time based timeout checking will add too much

	 * overhead on it. Usually the state changes in 1 or 2 loops on the

	 * test server, and we set 10000 times loop here for safety.

	 */

drivers/fpga/dfl.h

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@@ -232,7 +232,7 @@ struct dfl_feature_irq_ctx { 
 * @id: sub feature id.

 * @resource_index: each sub feature has one mmio resource for its registers.

 *		    this index is used to find its mmio resource from the

 *		    feature dev (platform device)'s reources.

 *		    feature dev (platform device)'s resources.

 * @ioaddr: mapped mmio resource address.

 * @irq_ctx: interrupt context list.

 * @nr_irqs: number of interrupt contexts.

drivers/fpga/fpga-bridge.c

+2 −2
Original line number Diff line number Diff line
@@ -230,7 +230,7 @@ EXPORT_SYMBOL_GPL(fpga_bridges_put); 
 *

 * Get an exclusive reference to the bridge and and it to the list.

 *

 * Return 0 for success, error code from of_fpga_bridge_get() othewise.

 * Return 0 for success, error code from of_fpga_bridge_get() otherwise.

 */

int of_fpga_bridge_get_to_list(struct device_node *np,

			       struct fpga_image_info *info,
@@ -260,7 +260,7 @@ EXPORT_SYMBOL_GPL(of_fpga_bridge_get_to_list); 
 *

 * Get an exclusive reference to the bridge and and it to the list.

 *

 * Return 0 for success, error code from fpga_bridge_get() othewise.

 * Return 0 for success, error code from fpga_bridge_get() otherwise.

 */

int fpga_bridge_get_to_list(struct device *dev,

			    struct fpga_image_info *info,