Commit 58f9466c authored by Ankit Nautiyal's avatar Ankit Nautiyal
Browse files

drm/i915/vrr: Make helpers for cmrr and vrr timings

parent 022d04b3
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+28 −17
Original line number Diff line number Diff line
@@ -222,6 +222,30 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
	return vtotal;
}

static
void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
{
	crtc_state->vrr.enable = true;
	crtc_state->cmrr.enable = true;
	/*
	 * TODO: Compute precise target refresh rate to determine
	 * if video_mode_required should be true. Currently set to
	 * false due to uncertainty about the precise target
	 * refresh Rate.
	 */
	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}

static
void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
{
	crtc_state->vrr.enable = true;
	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}

static
int intel_vrr_compute_vmin(struct intel_connector *connector,
			   const struct drm_display_mode *adjusted_mode)
@@ -298,23 +322,10 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
	 */
	crtc_state->vrr.vmin -= intel_vrr_flipline_offset(display);

	if (crtc_state->uapi.vrr_enabled) {
		crtc_state->vrr.enable = true;
		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
	} else if (is_cmrr_frac_required(crtc_state) && is_edp) {
		crtc_state->vrr.enable = true;
		crtc_state->cmrr.enable = true;
		/*
		 * TODO: Compute precise target refresh rate to determine
		 * if video_mode_required should be true. Currently set to
		 * false due to uncertainty about the precise target
		 * refresh Rate.
		 */
		crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
		crtc_state->vrr.vmin = crtc_state->vrr.vmax;
		crtc_state->vrr.flipline = crtc_state->vrr.vmin;
		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
	}
	if (crtc_state->uapi.vrr_enabled)
		intel_vrr_compute_vrr_timings(crtc_state);
	else if (is_cmrr_frac_required(crtc_state) && is_edp)
		intel_vrr_compute_cmrr_timings(crtc_state);

	if (HAS_AS_SDP(display)) {
		crtc_state->vrr.vsync_start =