Commit 5a1fef02 authored by Hansen's avatar Hansen Committed by Alex Deucher
Browse files

drm/amd/display: Fix detection of 4 lane for DPALT 



[Why]
DPALT detection for B0 PHY has its own set of RDPCSPIPE registers

[How]
Use RDPCSPIPE registers to detect if DPALT lane is 4 lane

Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: default avatarHansen <Hansen.Dsouza@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent a7e397b7

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c

+32 −1
Original line number Diff line number Diff line
@@ -63,6 +63,10 @@ 
#define AUX_REG_WRITE(reg_name, val) \

			dm_write_reg(CTX, AUX_REG(reg_name), val)



#ifndef MIN

#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))

#endif



void dcn31_link_encoder_set_dio_phy_mux(

	struct link_encoder *enc,

	enum encoder_type_select sel,
@@ -217,7 +221,7 @@ static const struct link_encoder_funcs dcn31_link_enc_funcs = { 
	.get_dig_frontend = dcn10_get_dig_frontend,

	.get_dig_mode = dcn10_get_dig_mode,

	.is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode,

	.get_max_link_cap = dcn20_link_encoder_get_max_link_cap,

	.get_max_link_cap = dcn31_link_encoder_get_max_link_cap,

	.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,

};
@@ -435,3 +439,30 @@ bool dcn31_link_encoder_is_in_alt_mode(struct link_encoder *enc) 


	return is_usb_c_alt_mode;

}



void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc,

										 struct dc_link_settings *link_settings)

{

	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);

	uint32_t is_in_usb_c_dp4_mode = 0;



	dcn10_link_encoder_get_max_link_cap(enc, link_settings);



	/* in usb c dp2 mode, max lane count is 2 */

	if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {

		if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {

			// [Note] no need to check hw_internal_rev once phy mux selection is ready

			REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);

		} else {

			if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A)

					|| (enc10->base.transmitter == TRANSMITTER_UNIPHY_B)

					|| (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {

				REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);

			} else {

				REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);

			}

		}

		if (!is_in_usb_c_dp4_mode)

			link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);

	}

}

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h

+3 −0
Original line number Diff line number Diff line
@@ -252,4 +252,7 @@ void dcn31_link_encoder_disable_output( 
bool dcn31_link_encoder_is_in_alt_mode(

	struct link_encoder *enc);



void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc,

	struct dc_link_settings *link_settings);



#endif /* __DC_LINK_ENCODER__DCN31_H__ */