Commit 5a2913aa authored by Le Ma's avatar Le Ma Committed by Alex Deucher
Browse files

drm/amd/pm: raise the deep sleep clock threshold for smu 13.0.6 



The DS clock may exceed the limit as sclk dfll divider is 16
to target freq.

Signed-off-by: default avatarLe Ma <le.ma@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarYang Wang <kevinyang.wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4eaa007c

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

+1 −1
Original line number Diff line number Diff line
@@ -94,7 +94,7 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_6.bin"); 
#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5

#define LINK_SPEED_MAX				4



#define SMU_13_0_6_DSCLK_THRESHOLD 100

#define SMU_13_0_6_DSCLK_THRESHOLD 140



#define MCA_BANK_IPID(_ip, _hwid, _type) \

	[AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, }